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Commit 9833d437 authored by Jishnu Prakash's avatar Jishnu Prakash
Browse files

dt-bindings: iio: Add PMIC5 GEN3 ADC support 



Add definitions for ADC channels for PMIC5 GEN3 ADC driver.
Add virtual channel definitions for PM5100, to be used
by ADC clients for PMIC5 GEN3.

Change-Id: I1180553c3ee697f994324c60ebfb4e996221108e
Signed-off-by: default avatarJishnu Prakash <jprakash@codeaurora.org>
parent 601026c7

include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm5100.h

0 → 100644
+83 −0
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/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2021 The Linux Foundation. All rights reserved.

 */



#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM5100_H

#define _DT_BINDINGS_QCOM_SPMI_VADC_PM5100_H



#ifndef PM5100_SID

#define PM5100_SID					0

#endif



/* ADC channels for PM5100_ADC for PMIC5 Gen3 */

#define PM5100_ADC5_GEN3_OFFSET_REF			(PM5100_SID << 8 | 0x0)

#define PM5100_ADC5_GEN3_1P25VREF			(PM5100_SID << 8 | 0x01)

#define PM5100_ADC5_GEN3_VREF_VADC			(PM5100_SID << 8 | 0x02)

#define PM5100_ADC5_GEN3_DIE_TEMP			(PM5100_SID << 8 | 0x03)



#define PM5100_ADC5_GEN3_AMUX1_THM			(PM5100_SID << 8 | 0x04)

#define PM5100_ADC5_GEN3_AMUX2_THM			(PM5100_SID << 8 | 0x05)

#define PM5100_ADC5_GEN3_AMUX3_THM			(PM5100_SID << 8 | 0x06)

#define PM5100_ADC5_GEN3_AMUX4_THM			(PM5100_SID << 8 | 0x07)

#define PM5100_ADC5_GEN3_AMUX5_THM			(PM5100_SID << 8 | 0x08)

#define PM5100_ADC5_GEN3_AMUX6_THM			(PM5100_SID << 8 | 0x09)

#define PM5100_ADC5_GEN3_AMUX1_GPIO10			(PM5100_SID << 8 | 0x0a)

#define PM5100_ADC5_GEN3_AMUX2_GPIO11			(PM5100_SID << 8 | 0x0b)

#define PM5100_ADC5_GEN3_AMUX3_GPIO			(PM5100_SID << 8 | 0x0c)

#define PM5100_ADC5_GEN3_AMUX4_GPIO			(PM5100_SID << 8 | 0x0d)



#define PM5100_ADC5_GEN3_CHG_TEMP			(PM5100_SID << 8 | 0x10)

#define PM5100_ADC5_GEN3_USB_SNS_V_16		(PM5100_SID << 8 | 0x11)

#define PM5100_ADC5_GEN3_VIN_DIV16_MUX			(PM5100_SID << 8 | 0x12)

#define PM5100_ADC5_GEN3_IIN_FB			(PM5100_SID << 8 | 0x17)

#define PM5100_ADC5_GEN3_ICHG_FB			(PM5100_SID << 8 | 0xa1)



/* 30k pull-up1 */

#define PM5100_ADC5_GEN3_AMUX1_THM_30K_PU		(PM5100_SID << 8 | 0x24)

#define PM5100_ADC5_GEN3_AMUX2_THM_30K_PU		(PM5100_SID << 8 | 0x25)

#define PM5100_ADC5_GEN3_AMUX3_THM_30K_PU		(PM5100_SID << 8 | 0x26)

#define PM5100_ADC5_GEN3_AMUX4_THM_30K_PU		(PM5100_SID << 8 | 0x27)

#define PM5100_ADC5_GEN3_AMUX5_THM_30K_PU		(PM5100_SID << 8 | 0x28)

#define PM5100_ADC5_GEN3_AMUX6_THM_30K_PU		(PM5100_SID << 8 | 0x29)

#define PM5100_ADC5_GEN3_AMUX1_GPIO10_30K_PU		(PM5100_SID << 8 | 0x2a)

#define PM5100_ADC5_GEN3_AMUX2_GPIO11_30K_PU		(PM5100_SID << 8 | 0x2b)

#define PM5100_ADC5_GEN3_AMUX3_GPIO_30K_PU		(PM5100_SID << 8 | 0x2c)

#define PM5100_ADC5_GEN3_AMUX4_GPIO_30K_PU		(PM5100_SID << 8 | 0x2d)





#define ADC5_GEN3_AMUX2_GPIO_100K_PU			0x4b





/* 100k pull-up2 */

#define PM5100_ADC5_GEN3_AMUX1_THM_100K_PU		(PM5100_SID << 8 | 0x44)

#define PM5100_ADC5_GEN3_AMUX2_THM_100K_PU		(PM5100_SID << 8 | 0x45)

#define PM5100_ADC5_GEN3_AMUX3_THM_100K_PU		(PM5100_SID << 8 | 0x46)

#define PM5100_ADC5_GEN3_AMUX4_THM_100K_PU		(PM5100_SID << 8 | 0x47)

#define PM5100_ADC5_GEN3_AMUX5_THM_100K_PU		(PM5100_SID << 8 | 0x48)

#define PM5100_ADC5_GEN3_AMUX6_THM_100K_PU		(PM5100_SID << 8 | 0x49)

#define PM5100_ADC5_GEN3_AMUX1_GPIO10_100K_PU		(PM5100_SID << 8 | 0x4a)

#define PM5100_ADC5_GEN3_AMUX2_GPIO11_100K_PU		(PM5100_SID << 8 | 0x4b)

#define PM5100_ADC5_GEN3_AMUX3_GPIO_100K_PU		(PM5100_SID << 8 | 0x4c)

#define PM5100_ADC5_GEN3_AMUX4_GPIO_100K_PU		(PM5100_SID << 8 | 0x4d)



/* 400k pull-up3 */

#define PM5100_ADC5_GEN3_AMUX1_THM_400K_PU		(PM5100_SID << 8 | 0x64)

#define PM5100_ADC5_GEN3_AMUX2_THM_400K_PU		(PM5100_SID << 8 | 0x65)

#define PM5100_ADC5_GEN3_AMUX3_THM_400K_PU		(PM5100_SID << 8 | 0x66)

#define PM5100_ADC5_GEN3_AMUX4_THM_400K_PU		(PM5100_SID << 8 | 0x67)

#define PM5100_ADC5_GEN3_AMUX5_THM_400K_PU		(PM5100_SID << 8 | 0x68)

#define PM5100_ADC5_GEN3_AMUX6_THM_400K_PU		(PM5100_SID << 8 | 0x69)

#define PM5100_ADC5_GEN3_AMUX1_GPIO10_400K_PU		(PM5100_SID << 8 | 0x6a)

#define PM5100_ADC5_GEN3_AMUX2_GPIO11_400K_PU		(PM5100_SID << 8 | 0x6b)

#define PM5100_ADC5_GEN3_AMUX3_GPIO_400K_PU		(PM5100_SID << 8 | 0x6c)

#define PM5100_ADC5_GEN3_AMUX4_GPIO_400K_PU		(PM5100_SID << 8 | 0x6d)



/* 1/3 Divider */

#define PM5100_ADC5_GEN3_GPIO10_DIV3			(PM5100_SID << 8 | 0x8a)

#define PM5100_ADC5_GEN3_GPIO11_DIV3			(PM5100_SID << 8 | 0x8b)



#define PM5100_ADC5_GEN3_VPH_PWR			(PM5100_SID << 8 | 0x8e)

#define PM5100_ADC5_GEN3_VBAT_SNS_QBG			(PM5100_SID << 8 | 0x8f)



#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM5100_H */

include/dt-bindings/iio/qcom,spmi-vadc.h

+78 −1
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (c) 2012-2014,2018-2020 The Linux Foundation. All rights reserved.

 * Copyright (c) 2012-2014,2018-2021 The Linux Foundation. All rights reserved.

 */



#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H
@@ -300,6 +300,83 @@ 
#define ADC7_SBUx				0x94

#define ADC7_VBAT_2S_MID			0x96



/* ADC channels for PMIC5 Gen3 */



#define ADC5_GEN3_OFFSET_REF			0x00

#define ADC5_GEN3_1P25VREF			0x01

#define ADC5_GEN3_VREF_VADC			0x02

#define ADC5_GEN3_DIE_TEMP			0x03



#define ADC5_GEN3_AMUX1_THM			0x04

#define ADC5_GEN3_AMUX2_THM			0x05

#define ADC5_GEN3_AMUX3_THM			0x06

#define ADC5_GEN3_AMUX4_THM			0x07

#define ADC5_GEN3_AMUX5_THM			0x08

#define ADC5_GEN3_AMUX6_THM			0x09

#define ADC5_GEN3_AMUX1_GPIO			0x0a

#define ADC5_GEN3_AMUX2_GPIO			0x0b

#define ADC5_GEN3_AMUX3_GPIO			0x0c

#define ADC5_GEN3_AMUX4_GPIO			0x0d



#define ADC5_GEN3_CHG_TEMP			0x10

#define ADC5_GEN3_USB_SNS_V_16			0x11

#define ADC5_GEN3_VIN_DIV16_MUX			0x12

#define ADC5_GEN3_VREF_BAT_THERM		0x15

#define ADC5_GEN3_IIN_FB			0x17

#define ADC5_GEN3_ICHG_SMB			0x18

#define ADC5_GEN3_IIN_SMB			0x19

#define ADC5_GEN3_ICHG_FB			0xa1



/* 30k pull-up1 */

#define ADC5_GEN3_AMUX1_THM_30K_PU		0x24

#define ADC5_GEN3_AMUX2_THM_30K_PU		0x25

#define ADC5_GEN3_AMUX3_THM_30K_PU		0x26

#define ADC5_GEN3_AMUX4_THM_30K_PU		0x27

#define ADC5_GEN3_AMUX5_THM_30K_PU		0x28

#define ADC5_GEN3_AMUX6_THM_30K_PU		0x29

#define ADC5_GEN3_AMUX1_GPIO_30K_PU		0x2a

#define ADC5_GEN3_AMUX2_GPIO_30K_PU		0x2b

#define ADC5_GEN3_AMUX3_GPIO_30K_PU		0x2c

#define ADC5_GEN3_AMUX4_GPIO_30K_PU		0x2d



/* 100k pull-up2 */

#define ADC5_GEN3_AMUX1_THM_100K_PU		0x44

#define ADC5_GEN3_AMUX2_THM_100K_PU		0x45

#define ADC5_GEN3_AMUX3_THM_100K_PU		0x46

#define ADC5_GEN3_AMUX4_THM_100K_PU		0x47

#define ADC5_GEN3_AMUX5_THM_100K_PU		0x48

#define ADC5_GEN3_AMUX6_THM_100K_PU		0x49

#define ADC5_GEN3_AMUX1_GPIO_100K_PU		0x4a

#define ADC5_GEN3_AMUX2_GPIO_100K_PU		0x4b

#define ADC5_GEN3_AMUX3_GPIO_100K_PU		0x4c

#define ADC5_GEN3_AMUX4_GPIO_100K_PU		0x4d



/* 400k pull-up3 */

#define ADC5_GEN3_AMUX1_THM_400K_PU		0x64

#define ADC5_GEN3_AMUX2_THM_400K_PU		0x65

#define ADC5_GEN3_AMUX3_THM_400K_PU		0x66

#define ADC5_GEN3_AMUX4_THM_400K_PU		0x67

#define ADC5_GEN3_AMUX5_THM_400K_PU		0x68

#define ADC5_GEN3_AMUX6_THM_400K_PU		0x69

#define ADC5_GEN3_AMUX1_GPIO_400K_PU		0x6a

#define ADC5_GEN3_AMUX2_GPIO_400K_PU		0x6b

#define ADC5_GEN3_AMUX3_GPIO_400K_PU		0x6c

#define ADC5_GEN3_AMUX4_GPIO_400K_PU		0x6d



/* 1/3 Divider */

#define ADC5_GEN3_AMUX1_GPIO_DIV3		0x8a

#define ADC5_GEN3_AMUX2_GPIO_DIV3		0x8b

#define ADC5_GEN3_AMUX3_GPIO_DIV3		0x8c



#define ADC5_GEN3_VPH_PWR			0x8e

#define ADC5_GEN3_VBAT_SNS_QBG			0x8f



#define ADC5_GEN3_VBAT_SNS_CHGR			0x94

#define ADC5_GEN3_VBAT_2S_MID_QBG		0x96

#define ADC5_GEN3_VBAT_2S_MID_CHGR		0x9d



#define ADC5_OFFSET_EXT2			0xf8



/* VADC scale function index */

#define ADC_SCALE_DEFAULT			0

#define ADC_SCALE_THERM_100K_PULLUP		1