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Commit 9826b113 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-fixes-4.20' of git://people.freedesktop.org/~agd5f/linux into drm-fixes 



Fixes for 4.20:
- Fix for huge page handling that caused a GPUVM fault in some cases
- Fix IH ring setup
- Fix for xgmi aperture setup
- Fix for watermark setup for SMU

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181114171853.2866-1-alexander.deucher@amd.com
parents 7b74026d c1a17777

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

+10 −8
Original line number Diff line number Diff line
@@ -1632,13 +1632,6 @@ static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, 
			continue;

		}



		/* First check if the entry is already handled */

		if (cursor.pfn < frag_start) {

			cursor.entry->huge = true;

			amdgpu_vm_pt_next(adev, &cursor);

			continue;

		}



		/* If it isn't already handled it can't be a huge page */

		if (cursor.entry->huge) {

			/* Add the entry to the relocated list to update it. */
@@ -1701,10 +1694,19 @@ static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, 
			}

		} while (frag_start < entry_end);



		if (frag >= shift)

		if (amdgpu_vm_pt_descendant(adev, &cursor)) {

			/* Mark all child entries as huge */

			while (cursor.pfn < frag_start) {

				cursor.entry->huge = true;

				amdgpu_vm_pt_next(adev, &cursor);

			}



		} else if (frag >= shift) {

			/* or just move on to the next on the same level. */

			amdgpu_vm_pt_next(adev, &cursor);

		}

	}



	return 0;

}

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

+3 −3
Original line number Diff line number Diff line
@@ -72,7 +72,7 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) 


	/* Program the system aperture low logical page number. */

	WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,

		     min(adev->gmc.vram_start, adev->gmc.agp_start) >> 18);

		     min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);



	if (adev->asic_type == CHIP_RAVEN && adev->rev_id >= 0x8)

		/*
@@ -82,11 +82,11 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) 
		 * to get rid of the VM fault and hardware hang.

		 */

		WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,

			     max((adev->gmc.vram_end >> 18) + 0x1,

			     max((adev->gmc.fb_end >> 18) + 0x1,

				 adev->gmc.agp_end >> 18));

	else

		WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,

			     max(adev->gmc.vram_end, adev->gmc.agp_end) >> 18);

			     max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);



	/* Set default page address. */

	value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

+3 −3
Original line number Diff line number Diff line
@@ -90,7 +90,7 @@ static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) 


	/* Program the system aperture low logical page number. */

	WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,

		     min(adev->gmc.vram_start, adev->gmc.agp_start) >> 18);

		     min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);



	if (adev->asic_type == CHIP_RAVEN && adev->rev_id >= 0x8)

		/*
@@ -100,11 +100,11 @@ static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) 
		 * to get rid of the VM fault and hardware hang.

		 */

		WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,

			     max((adev->gmc.vram_end >> 18) + 0x1,

			     max((adev->gmc.fb_end >> 18) + 0x1,

				 adev->gmc.agp_end >> 18));

	else

		WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,

			     max(adev->gmc.vram_end, adev->gmc.agp_end) >> 18);

			     max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);



	/* Set default page address. */

	value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

+1 −1
Original line number Diff line number Diff line
@@ -129,7 +129,7 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) 
	else

		wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);

	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));

	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);

	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFFFF);



	/* set rptr, wptr to 0 */

	WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);

drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c

+16 −16
Original line number Diff line number Diff line
@@ -713,20 +713,20 @@ int smu_set_watermarks_for_clocks_ranges(void *wt_table, 
	for (i = 0; i < wm_with_clock_ranges->num_wm_dmif_sets; i++) {

		table->WatermarkRow[1][i].MinClock =

			cpu_to_le16((uint16_t)

			(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz) /

			1000);

			(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /

			1000));

		table->WatermarkRow[1][i].MaxClock =

			cpu_to_le16((uint16_t)

			(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz) /

			1000);

			(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /

			1000));

		table->WatermarkRow[1][i].MinUclk =

			cpu_to_le16((uint16_t)

			(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz) /

			1000);

			(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /

			1000));

		table->WatermarkRow[1][i].MaxUclk =

			cpu_to_le16((uint16_t)

			(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz) /

			1000);

			(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /

			1000));

		table->WatermarkRow[1][i].WmSetting = (uint8_t)

				wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;

	}
@@ -734,20 +734,20 @@ int smu_set_watermarks_for_clocks_ranges(void *wt_table, 
	for (i = 0; i < wm_with_clock_ranges->num_wm_mcif_sets; i++) {

		table->WatermarkRow[0][i].MinClock =

			cpu_to_le16((uint16_t)

			(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz) /

			1000);

			(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /

			1000));

		table->WatermarkRow[0][i].MaxClock =

			cpu_to_le16((uint16_t)

			(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz) /

			1000);

			(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /

			1000));

		table->WatermarkRow[0][i].MinUclk =

			cpu_to_le16((uint16_t)

			(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz) /

			1000);

			(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /

			1000));

		table->WatermarkRow[0][i].MaxUclk =

			cpu_to_le16((uint16_t)

			(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz) /

			1000);

			(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /

			1000));

		table->WatermarkRow[0][i].WmSetting = (uint8_t)

				wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;

	}