clk: qcom: Add support for VIDEOCC clock driver for SHIMA (980834c9) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/clk/qcom/Kconfig

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		@@ -411,4 +411,13 @@ config SM_GCC_SHIMA
		Say Y if you want to use peripheral devices such as UART, SPI, I2C,
		USB, UFS, SD/eMMC, PCIe, etc.

		config SM_VIDEOCC_SHIMA
		tristate "SHIMA Video Clock Controller"
		depends on SM_GCC_SHIMA
		help
		Support for the video clock controller on Qualcomm Technologies, Inc.
		SHIMA devices.
		Say Y if you want to support video devices and functionality such as
		video encode/decode.

		endif

drivers/clk/qcom/Makefile

+1 −0

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		@@ -64,6 +64,7 @@ obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
		obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
		obj-$(CONFIG_SM_GCC_HOLI) += gcc-holi.o
		obj-$(CONFIG_SM_GCC_SHIMA) += gcc-shima.o
		obj-$(CONFIG_SM_VIDEOCC_SHIMA) += videocc-shima.o
		obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
		obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
		obj-$(CONFIG_QCOM_HFPLL) += hfpll.o

drivers/clk/qcom/videocc-shima.c

0 → 100644

+617 −0

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0-only
		/*
		* Copyright (c) 2020, The Linux Foundation. All rights reserved.
		*/

		#include <linux/clk-provider.h>
		#include <linux/kernel.h>
		#include <linux/module.h>
		#include <linux/of_device.h>
		#include <linux/of.h>
		#include <linux/regmap.h>

		#include <dt-bindings/clock/qcom,videocc-shima.h>

		#include "clk-alpha-pll.h"
		#include "clk-branch.h"
		#include "clk-rcg.h"
		#include "clk-regmap-divider.h"
		#include "common.h"
		#include "reset.h"
		#include "vdd-level.h"

		static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner);
		static DEFINE_VDD_REGULATORS(vdd_mx, VDD_NUM, 1, vdd_corner);

		enum {
		P_BI_TCXO,
		P_CORE_BI_PLL_TEST_SE,
		P_SLEEP_CLK,
		P_VIDEO_PLL0_OUT_MAIN,
		P_VIDEO_PLL1_OUT_MAIN,
		};

		static struct pll_vco lucid_5lpe_vco[] = {
		{ 249600000, 1750000000, 0 },
		};

		static const struct alpha_pll_config video_pll0_config = {
		.l = 0x25,
		.alpha = 0x8000,
		.config_ctl_val = 0x20485699,
		.config_ctl_hi_val = 0x00002261,
		.config_ctl_hi1_val = 0x2A9A699C,
		.test_ctl_val = 0x00000000,
		.test_ctl_hi_val = 0x00000000,
		.test_ctl_hi1_val = 0x01800000,
		.user_ctl_val = 0x00000001,
		.user_ctl_hi_val = 0x00000805,
		.user_ctl_hi1_val = 0x00000000,
		};

		static struct clk_alpha_pll video_pll0 = {
		.offset = 0x42c,
		.vco_table = lucid_5lpe_vco,
		.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
		.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_5LPE],
		.clkr = {
		.hw.init = &(struct clk_init_data){
		.name = "video_pll0",
		.parent_data = &(const struct clk_parent_data){
		.fw_name = "bi_tcxo",
		},
		.num_parents = 1,
		.ops = &clk_alpha_pll_lucid_5lpe_ops,
		},
		.vdd_data = {
		.vdd_class = &vdd_mx,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_MIN] = 615000000,
		[VDD_LOW] = 1066000000,
		[VDD_LOW_L1] = 1500000000,
		[VDD_NOMINAL] = 1750000000},
		},
		},
		};

		static const struct alpha_pll_config video_pll1_config = {
		.l = 0x2B,
		.alpha = 0xC000,
		.config_ctl_val = 0x20485699,
		.config_ctl_hi_val = 0x00002261,
		.config_ctl_hi1_val = 0x2A9A699C,
		.test_ctl_val = 0x00000000,
		.test_ctl_hi_val = 0x00000000,
		.test_ctl_hi1_val = 0x01800000,
		.user_ctl_val = 0x00000001,
		.user_ctl_hi_val = 0x00000805,
		.user_ctl_hi1_val = 0x00000000,
		};

		static struct clk_alpha_pll video_pll1 = {
		.offset = 0x7d0,
		.vco_table = lucid_5lpe_vco,
		.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
		.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_5LPE],
		.clkr = {
		.hw.init = &(struct clk_init_data){
		.name = "video_pll1",
		.parent_data = &(const struct clk_parent_data){
		.fw_name = "bi_tcxo",
		},
		.num_parents = 1,
		.ops = &clk_alpha_pll_lucid_5lpe_ops,
		},
		.vdd_data = {
		.vdd_class = &vdd_mx,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_MIN] = 615000000,
		[VDD_LOW] = 1066000000,
		[VDD_LOW_L1] = 1500000000,
		[VDD_NOMINAL] = 1750000000},
		},
		},
		};

		static const struct parent_map video_cc_parent_map_0[] = {
		{ P_BI_TCXO, 0 },
		{ P_CORE_BI_PLL_TEST_SE, 7 },
		};

		static const struct clk_parent_data video_cc_parent_data_0_ao[] = {
		{ .fw_name = "bi_tcxo_ao", },
		{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
		};

		static const struct parent_map video_cc_parent_map_1[] = {
		{ P_BI_TCXO, 0 },
		{ P_VIDEO_PLL0_OUT_MAIN, 1 },
		{ P_CORE_BI_PLL_TEST_SE, 7 },
		};

		static const struct clk_parent_data video_cc_parent_data_1[] = {
		{ .fw_name = "bi_tcxo", },
		{ .hw = &video_pll0.clkr.hw },
		{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
		};

		static const struct parent_map video_cc_parent_map_2[] = {
		{ P_BI_TCXO, 0 },
		{ P_VIDEO_PLL1_OUT_MAIN, 1 },
		{ P_CORE_BI_PLL_TEST_SE, 7 },
		};

		static const struct clk_parent_data video_cc_parent_data_2[] = {
		{ .fw_name = "bi_tcxo", },
		{ .hw = &video_pll1.clkr.hw },
		{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
		};

		static const struct parent_map video_cc_parent_map_3[] = {
		{ P_SLEEP_CLK, 0 },
		{ P_CORE_BI_PLL_TEST_SE, 7 },
		};

		static const struct clk_parent_data video_cc_parent_data_3[] = {
		{ .fw_name = "sleep_clk", },
		{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
		};

		static const struct freq_tbl ftbl_video_cc_ahb_clk_src[] = {
		F(19200000, P_BI_TCXO, 1, 0, 0),
		{ }
		};

		static struct clk_rcg2 video_cc_ahb_clk_src = {
		.cmd_rcgr = 0xbd4,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = video_cc_parent_map_0,
		.freq_tbl = ftbl_video_cc_ahb_clk_src,
		.enable_safe_config = true,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "video_cc_ahb_clk_src",
		.parent_data = video_cc_parent_data_0_ao,
		.num_parents = 2,
		.ops = &clk_rcg2_ops,
		},
		};

		static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
		F(720000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
		F(1014000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
		F(1098000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
		F(1332000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
		{ }
		};

		static struct clk_rcg2 video_cc_mvs0_clk_src = {
		.cmd_rcgr = 0xb94,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = video_cc_parent_map_1,
		.freq_tbl = ftbl_video_cc_mvs0_clk_src,
		.enable_safe_config = true,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "video_cc_mvs0_clk_src",
		.parent_data = video_cc_parent_data_1,
		.num_parents = 3,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_rcg2_ops,
		},
		.clkr.vdd_data = {
		.vdd_class = &vdd_mx,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_LOWER] = 720000000,
		[VDD_LOW] = 1014000000,
		[VDD_LOW_L1] = 1098000000,
		[VDD_NOMINAL] = 1332000000},
		},
		};

		static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = {
		F(840000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
		F(1098000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
		F(1332000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
		{ }
		};

		static struct clk_rcg2 video_cc_mvs1_clk_src = {
		.cmd_rcgr = 0xbb4,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = video_cc_parent_map_2,
		.freq_tbl = ftbl_video_cc_mvs1_clk_src,
		.enable_safe_config = true,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "video_cc_mvs1_clk_src",
		.parent_data = video_cc_parent_data_2,
		.num_parents = 3,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_rcg2_ops,
		},
		.clkr.vdd_data = {
		.vdd_class = &vdd_mx,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_LOWER] = 840000000,
		[VDD_LOW] = 1098000000,
		[VDD_NOMINAL] = 1332000000},
		},
		};

		static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] = {
		F(32000, P_SLEEP_CLK, 1, 0, 0),
		{ }
		};

		static struct clk_rcg2 video_cc_sleep_clk_src = {
		.cmd_rcgr = 0xef0,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = video_cc_parent_map_3,
		.freq_tbl = ftbl_video_cc_sleep_clk_src,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "video_cc_sleep_clk_src",
		.parent_data = video_cc_parent_data_3,
		.num_parents = 2,
		.ops = &clk_rcg2_ops,
		},
		.clkr.vdd_data = {
		.vdd_class = &vdd_cx,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_LOWER] = 32000},
		},
		};

		static struct clk_rcg2 video_cc_xo_clk_src = {
		.cmd_rcgr = 0xecc,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = video_cc_parent_map_0,
		.freq_tbl = ftbl_video_cc_ahb_clk_src,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "video_cc_xo_clk_src",
		.parent_data = video_cc_parent_data_0_ao,
		.num_parents = 2,
		.ops = &clk_rcg2_ops,
		},
		};

		static struct clk_regmap_div video_cc_mvs0_div_clk_src = {
		.reg = 0xd54,
		.shift = 0,
		.width = 4,
		.clkr.hw.init = &(struct clk_init_data) {
		.name = "video_cc_mvs0_div_clk_src",
		.parent_data = &(const struct clk_parent_data){
		.hw = &video_cc_mvs0_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_regmap_div_ro_ops,
		},
		};

		static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = {
		.reg = 0xc54,
		.shift = 0,
		.width = 4,
		.clkr.hw.init = &(struct clk_init_data) {
		.name = "video_cc_mvs0c_div2_div_clk_src",
		.parent_data = &(const struct clk_parent_data){
		.hw = &video_cc_mvs0_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_regmap_div_ro_ops,
		},
		};

		static struct clk_regmap_div video_cc_mvs1_div_clk_src = {
		.reg = 0xdd4,
		.shift = 0,
		.width = 4,
		.clkr.hw.init = &(struct clk_init_data) {
		.name = "video_cc_mvs1_div_clk_src",
		.parent_data = &(const struct clk_parent_data){
		.hw = &video_cc_mvs1_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_regmap_div_ro_ops,
		},
		};

		static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = {
		.reg = 0xcf4,
		.shift = 0,
		.width = 4,
		.clkr.hw.init = &(struct clk_init_data) {
		.name = "video_cc_mvs1c_div2_div_clk_src",
		.parent_data = &(const struct clk_parent_data){
		.hw = &video_cc_mvs1_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_regmap_div_ro_ops,
		},
		};

		static struct clk_branch video_cc_ahb_clk = {
		.halt_reg = 0xe58,
		.halt_check = BRANCH_HALT,
		.hwcg_reg = 0xe58,
		.hwcg_bit = 1,
		.clkr = {
		.enable_reg = 0xe58,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "video_cc_ahb_clk",
		.parent_data = &(const struct clk_parent_data){
		.hw = &video_cc_ahb_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_IS_CRITICAL \| CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch video_cc_mvs0_clk = {
		.halt_reg = 0xd34,
		.halt_check = BRANCH_HALT_VOTED,
		.hwcg_reg = 0xd34,
		.hwcg_bit = 1,
		.clkr = {
		.enable_reg = 0xd34,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "video_cc_mvs0_clk",
		.parent_data = &(const struct clk_parent_data){
		.hw = &video_cc_mvs0_div_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch video_cc_mvs0c_clk = {
		.halt_reg = 0xc34,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0xc34,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "video_cc_mvs0c_clk",
		.parent_data = &(const struct clk_parent_data){
		.hw = &video_cc_mvs0c_div2_div_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch video_cc_mvs1_clk = {
		.halt_reg = 0xdb4,
		.halt_check = BRANCH_HALT_VOTED,
		.hwcg_reg = 0xdb4,
		.hwcg_bit = 1,
		.clkr = {
		.enable_reg = 0xdb4,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "video_cc_mvs1_clk",
		.parent_data = &(const struct clk_parent_data){
		.hw = &video_cc_mvs1_div_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch video_cc_mvs1_div2_clk = {
		.halt_reg = 0xdf4,
		.halt_check = BRANCH_HALT_VOTED,
		.hwcg_reg = 0xdf4,
		.hwcg_bit = 1,
		.clkr = {
		.enable_reg = 0xdf4,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "video_cc_mvs1_div2_clk",
		.parent_data = &(const struct clk_parent_data){
		.hw = &video_cc_mvs1c_div2_div_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch video_cc_mvs1c_clk = {
		.halt_reg = 0xcd4,
		.halt_check = BRANCH_HALT_VOTED,
		.clkr = {
		.enable_reg = 0xcd4,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "video_cc_mvs1c_clk",
		.parent_data = &(const struct clk_parent_data){
		.hw = &video_cc_mvs1c_div2_div_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch video_cc_sleep_clk = {
		.halt_reg = 0xf10,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0xf10,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "video_cc_sleep_clk",
		.parent_data = &(const struct clk_parent_data){
		.hw = &video_cc_sleep_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch video_cc_xo_clk = {
		.halt_reg = 0xeec,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0xeec,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "video_cc_xo_clk",
		.parent_data = &(const struct clk_parent_data){
		.hw = &video_cc_xo_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_IS_CRITICAL \| CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_regmap *video_cc_shima_clocks[] = {
		[VIDEO_CC_AHB_CLK] = &video_cc_ahb_clk.clkr,
		[VIDEO_CC_AHB_CLK_SRC] = &video_cc_ahb_clk_src.clkr,
		[VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
		[VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
		[VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr,
		[VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
		[VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] =
		&video_cc_mvs0c_div2_div_clk_src.clkr,
		[VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr,
		[VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr,
		[VIDEO_CC_MVS1_DIV2_CLK] = &video_cc_mvs1_div2_clk.clkr,
		[VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr,
		[VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr,
		[VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] =
		&video_cc_mvs1c_div2_div_clk_src.clkr,
		[VIDEO_CC_SLEEP_CLK] = &video_cc_sleep_clk.clkr,
		[VIDEO_CC_SLEEP_CLK_SRC] = &video_cc_sleep_clk_src.clkr,
		[VIDEO_CC_XO_CLK] = &video_cc_xo_clk.clkr,
		[VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr,
		[VIDEO_PLL0] = &video_pll0.clkr,
		[VIDEO_PLL1] = &video_pll1.clkr,
		};

		static const struct qcom_reset_map video_cc_shima_resets[] = {
		[CVP_VIDEO_CC_INTERFACE_BCR] = { 0xe54 },
		[CVP_VIDEO_CC_MVS0_BCR] = { 0xd14 },
		[VIDEO_CC_MVS0C_CLK_ARES] = { 0xc34, 2 },
		[CVP_VIDEO_CC_MVS0C_BCR] = { 0xbf4 },
		[CVP_VIDEO_CC_MVS1_BCR] = { 0xd94 },
		[VIDEO_CC_MVS1C_CLK_ARES] = { 0xcd4, 2 },
		[CVP_VIDEO_CC_MVS1C_BCR] = { 0xc94 },
		};

		static const struct regmap_config video_cc_shima_regmap_config = {
		.reg_bits = 32,
		.reg_stride = 4,
		.val_bits = 32,
		.max_register = 0xf4c,
		.fast_io = true,
		};

		static const struct qcom_cc_desc video_cc_shima_desc = {
		.config = &video_cc_shima_regmap_config,
		.clks = video_cc_shima_clocks,
		.num_clks = ARRAY_SIZE(video_cc_shima_clocks),
		.resets = video_cc_shima_resets,
		.num_resets = ARRAY_SIZE(video_cc_shima_resets),
		};

		static const struct of_device_id video_cc_shima_match_table[] = {
		{ .compatible = "qcom,shima-videocc" },
		{ }
		};
		MODULE_DEVICE_TABLE(of, video_cc_shima_match_table);

		static int video_cc_shima_probe(struct platform_device *pdev)
		{
		struct regmap *regmap;
		int ret;

		vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx");
		if (IS_ERR(vdd_cx.regulator[0])) {
		if (PTR_ERR(vdd_cx.regulator[0]) != -EPROBE_DEFER)
		dev_err(&pdev->dev, "Unable to get vdd_cx regulator\n");
		return PTR_ERR(vdd_cx.regulator[0]);
		}

		vdd_mx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mx");
		if (IS_ERR(vdd_mx.regulator[0])) {
		if (PTR_ERR(vdd_mx.regulator[0]) != -EPROBE_DEFER)
		dev_err(&pdev->dev, "Unable to get vdd_mx regulator\n");
		return PTR_ERR(vdd_mx.regulator[0]);
		}

		regmap = qcom_cc_map(pdev, &video_cc_shima_desc);
		if (IS_ERR(regmap))
		return PTR_ERR(regmap);

		clk_lucid_5lpe_pll_configure(&video_pll0, regmap, &video_pll0_config);
		clk_lucid_5lpe_pll_configure(&video_pll1, regmap, &video_pll1_config);

		ret = qcom_cc_really_probe(pdev, &video_cc_shima_desc, regmap);
		if (ret) {
		dev_err(&pdev->dev, "Failed to register VIDEO CC clocks\n");
		return ret;
		}

		dev_info(&pdev->dev, "Registered VIDEO CC clocks\n");

		return ret;
		}

		static void video_cc_shima_sync_state(struct device *dev)
		{
		qcom_cc_sync_state(dev, &video_cc_shima_desc);
		}

		static struct platform_driver video_cc_shima_driver = {
		.probe = video_cc_shima_probe,
		.driver = {
		.name = "video_cc-shima",
		.of_match_table = video_cc_shima_match_table,
		.sync_state = video_cc_shima_sync_state,
		},
		};

		static int __init video_cc_shima_init(void)
		{
		return platform_driver_register(&video_cc_shima_driver);
		}
		subsys_initcall(video_cc_shima_init);

		static void __exit video_cc_shima_exit(void)
		{
		platform_driver_unregister(&video_cc_shima_driver);
		}
		module_exit(video_cc_shima_exit);

		MODULE_DESCRIPTION("QTI VIDEO_CC SHIMA Driver");
		MODULE_LICENSE("GPL v2");