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Commit 97ee6e92 authored by Daniele Ceraolo Spurio's avatar Daniele Ceraolo Spurio Committed by Chris Wilson
Browse files

drm/i915: stop storing the media fuse 



We're already updating the engine_mask to reflect what's in the HW, so
we can just get the info from there. A couple of macros have been added
to facilitate this.

v2: Appease checkpatch

Suggested-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarMichal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190322002431.9585-1-daniele.ceraolospurio@intel.com
parent b024ab9b

drivers/gpu/drm/i915/i915_drv.h

+11 −0
Original line number Diff line number Diff line
@@ -2454,6 +2454,17 @@ static inline unsigned int i915_sg_segment_size(void) 
#define ALL_ENGINES	(~0u)

#define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id))



#define ENGINE_INSTANCES_MASK(dev_priv, first, count) ({		\

	unsigned int first__ = (first);					\

	unsigned int count__ = (count);					\

	(INTEL_INFO(dev_priv)->engine_mask &				\

	 GENMASK(first__ + count__ - 1, first__)) >> first__		\

})

#define VDBOX_MASK(dev_priv) \

	ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS)

#define VEBOX_MASK(dev_priv) \

	ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS)



#define HAS_LLC(dev_priv)	(INTEL_INFO(dev_priv)->has_llc)

#define HAS_SNOOP(dev_priv)	(INTEL_INFO(dev_priv)->has_snoop)

#define HAS_EDRAM(dev_priv)	(!!((dev_priv)->edram_cap & EDRAM_ENABLED))

drivers/gpu/drm/i915/intel_device_info.c

+9 −7
Original line number Diff line number Diff line
@@ -878,22 +878,24 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) 
	unsigned int logical_vdbox = 0;

	unsigned int i;

	u32 media_fuse;

	u16 vdbox_mask;

	u16 vebox_mask;



	if (INTEL_GEN(dev_priv) < 11)

		return;



	media_fuse = ~I915_READ(GEN11_GT_VEBOX_VDBOX_DISABLE);



	RUNTIME_INFO(dev_priv)->vdbox_enable = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;

	RUNTIME_INFO(dev_priv)->vebox_enable = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>

	vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;

	vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>

		      GEN11_GT_VEBOX_DISABLE_SHIFT;



	DRM_DEBUG_DRIVER("vdbox enable: %04x\n", RUNTIME_INFO(dev_priv)->vdbox_enable);

	DRM_DEBUG_DRIVER("vdbox enable: %04x\n", vdbox_mask);

	for (i = 0; i < I915_MAX_VCS; i++) {

		if (!HAS_ENGINE(dev_priv, _VCS(i)))

			continue;



		if (!(BIT(i) & RUNTIME_INFO(dev_priv)->vdbox_enable)) {

		if (!(BIT(i) & vdbox_mask)) {

			info->engine_mask &= ~BIT(_VCS(i));

			DRM_DEBUG_DRIVER("vcs%u fused off\n", i);

			continue;
@@ -907,12 +909,12 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) 
			RUNTIME_INFO(dev_priv)->vdbox_sfc_access |= BIT(i);

	}



	DRM_DEBUG_DRIVER("vebox enable: %04x\n", RUNTIME_INFO(dev_priv)->vebox_enable);

	DRM_DEBUG_DRIVER("vebox enable: %04x\n", vebox_mask);

	for (i = 0; i < I915_MAX_VECS; i++) {

		if (!HAS_ENGINE(dev_priv, _VECS(i)))

			continue;



		if (!(BIT(i) & RUNTIME_INFO(dev_priv)->vebox_enable)) {

		if (!(BIT(i) & vebox_mask)) {

			info->engine_mask &= ~BIT(_VECS(i));

			DRM_DEBUG_DRIVER("vecs%u fused off\n", i);

		}

drivers/gpu/drm/i915/intel_device_info.h

+0 −4
Original line number Diff line number Diff line
@@ -209,10 +209,6 @@ struct intel_runtime_info { 


	u32 cs_timestamp_frequency_khz;



	/* Enabled (not fused off) media engine bitmasks. */

	u8 vdbox_enable;

	u8 vebox_enable;



	/* Media engine access to SFC per instance */

	u8 vdbox_sfc_access;

};