ARM: dts: msm: Update capacity-dmips-mhz values for Shima

Update capacity-dmips-mhz value for prime CPU in Shima.

Change-Id: I61f5a5229d9f8564b6a47bba25177c743a954319

parent 9269fc11

qcom/shima.dtsi

+1 −1

Original line number	Diff line number	Diff line
		@@ -162,7 +162,7 @@
		reg = <0x0 0x700>;
		enable-method = "psci";
		qcom,freq-domain = <&cpufreq_hw 2 4>;
		capacity-dmips-mhz = <1946>;
		capacity-dmips-mhz = <1985>;
		dynamic-power-coefficient = <552>;
		cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
		next-level-cache = <&L2_7>;