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Commit 9735b04d authored by Sagar Arun Kamble's avatar Sagar Arun Kamble Committed by Chris Wilson
Browse files

drm/i915: Initialize pm_intr_keep during intel_irq_init for GuC 



Driver needs to ensure that it doesn't mask the PM interrupts, which are
unmasked/needed by GuC firmware. For that, Driver maintains a bitmask of
interrupts to be kept unmasked, pm_intr_keep.

pm_intr_keep was determined across GuC load. GuC gets loaded in different
scenarios and it is not going to change the pm_intr_keep so this patch
moves its setup to intel_irq_init.

This patch fixes incorrect RPS masking leading to UP interrupts triggered
even when at cur_freq=max and inversly for Down interrupts.

Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Michal Winiarski <michal.winiarski@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: default avatarSagar Arun Kamble <sagar.a.kamble@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1488862355-9768-1-git-send-email-sagar.a.kamble@intel.com
parent d38146b9

drivers/gpu/drm/i915/i915_irq.c

+24 −0
Original line number Diff line number Diff line
@@ -4301,6 +4301,30 @@ void intel_irq_init(struct drm_i915_private *dev_priv) 
	if (INTEL_INFO(dev_priv)->gen >= 8)

		dev_priv->rps.pm_intr_keep |= GEN8_PMINTR_REDIRECT_TO_GUC;



	/*

	 * The REDIRECT_TO_GUC bit of the PMINTRMSK register directs all

	 * (unmasked) PM interrupts to the GuC. All other bits of this

	 * register *disable* generation of a specific interrupt.

	 *

	 * 'pm_intr_keep' indicates bits that are NOT to be set when

	 * writing to the PM interrupt mask register, i.e. interrupts

	 * that must not be disabled.

	 *

	 * If the GuC is handling these interrupts, then we must not let

	 * the PM code disable ANY interrupt that the GuC is expecting.

	 * So for each ENABLED (0) bit in this register, we must SET the

	 * bit in pm_intr_keep so that it's left enabled for the GuC.

	 * GuC needs ARAT expired interrupt unmasked hence it is set in

	 * pm_intr_keep.

	 *

	 * Here we CLEAR REDIRECT_TO_GUC bit in pm_intr_keep, which will

	 * result in the register bit being left SET!

	 */

	if (HAS_GUC_SCHED(dev_priv)) {

		dev_priv->rps.pm_intr_keep |= ARAT_EXPIRED_INTRMSK;

		dev_priv->rps.pm_intr_keep &= ~GEN8_PMINTR_REDIRECT_TO_GUC;

	}



	if (IS_GEN2(dev_priv)) {

		/* Gen2 doesn't have a hardware frame counter */

		dev->max_vblank_count = 0;

drivers/gpu/drm/i915/i915_reg.h

+2 −1
Original line number Diff line number Diff line
@@ -7454,6 +7454,7 @@ enum { 
#define GEN6_RC6pp_THRESHOLD			_MMIO(0xA0C0)

#define GEN6_PMINTRMSK				_MMIO(0xA168)

#define   GEN8_PMINTR_REDIRECT_TO_GUC		(1<<31)

#define   ARAT_EXPIRED_INTRMSK			(1<<9)

#define GEN8_MISC_CTRL0				_MMIO(0xA180)

#define VLV_PWRDWNUPCTL				_MMIO(0xA294)

#define GEN9_MEDIA_PG_IDLE_HYSTERESIS		_MMIO(0xA0C4)

drivers/gpu/drm/i915/intel_guc_loader.c

+0 −26
Original line number Diff line number Diff line
@@ -114,7 +114,6 @@ static void guc_interrupts_capture(struct drm_i915_private *dev_priv) 
	struct intel_engine_cs *engine;

	enum intel_engine_id id;

	int irqs;

	u32 tmp;



	/* tell all command streamers to forward interrupts (but not vblank) to GuC */

	irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
@@ -128,31 +127,6 @@ static void guc_interrupts_capture(struct drm_i915_private *dev_priv) 
	I915_WRITE(GUC_BCS_RCS_IER, ~irqs);

	I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs);

	I915_WRITE(GUC_WD_VECS_IER, ~irqs);



	/*

	 * The REDIRECT_TO_GUC bit of the PMINTRMSK register directs all

	 * (unmasked) PM interrupts to the GuC. All other bits of this

	 * register *disable* generation of a specific interrupt.

	 *

	 * 'pm_intr_keep' indicates bits that are NOT to be set when

	 * writing to the PM interrupt mask register, i.e. interrupts

	 * that must not be disabled.

	 *

	 * If the GuC is handling these interrupts, then we must not let

	 * the PM code disable ANY interrupt that the GuC is expecting.

	 * So for each ENABLED (0) bit in this register, we must SET the

	 * bit in pm_intr_keep so that it's left enabled for the GuC.

	 *

	 * OTOH the REDIRECT_TO_GUC bit is initially SET in pm_intr_keep

	 * (so interrupts go to the DISPLAY unit at first); but here we

	 * need to CLEAR that bit, which will result in the register bit

	 * being left SET!

	 */

	tmp = I915_READ(GEN6_PMINTRMSK);

	if (tmp & GEN8_PMINTR_REDIRECT_TO_GUC) {

		dev_priv->rps.pm_intr_keep |= ~tmp;

		dev_priv->rps.pm_intr_keep &= ~GEN8_PMINTR_REDIRECT_TO_GUC;

	}

}



static u32 get_gttype(struct drm_i915_private *dev_priv)