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Commit 970ce66a authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge 5.4.175 into android11-5.4-lts 



Changes in 5.4.175
	drm/i915: Flush TLBs before releasing backing store
	rcu: Tighten rcu_advance_cbs_nowake() checks
	pinctrl: bcm2835: Drop unused define
	pinctrl: bcm2835: Refactor platform data
	pinctrl: bcm2835: Add support for all GPIOs on BCM2711
	pinctrl: bcm2835: Match BCM7211 compatible string
	pinctrl: bcm2835: Add support for wake-up interrupts
	pinctrl: bcm2835: Change init order for gpio hogs
	ARM: dts: gpio-ranges property is now required
	mmc: sdhci-esdhc-imx: disable CMDQ support
	select: Fix indefinitely sleeping task in poll_schedule_timeout()
	drm/vmwgfx: Fix stale file descriptors on failed usercopy
	Linux 5.4.175

Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@google.com>
Change-Id: Idbc458768ac31c010d89fefd97fc7b76efe03802
parents a075d1be 7cdf2951

Makefile

+1 −1
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

VERSION = 5

PATCHLEVEL = 4

SUBLEVEL = 174

SUBLEVEL = 175

EXTRAVERSION =

NAME = Kleptomaniac Octopus

arch/arm/boot/dts/bcm283x.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -183,6 +183,7 @@ 


			interrupt-controller;

			#interrupt-cells = <2>;

			gpio-ranges = <&gpio 0 0 54>;



			/* Defines pin muxing groups according to

			 * BCM2835-ARM-Peripherals.pdf page 102.

drivers/gpu/drm/i915/gem/i915_gem_object_types.h

+3 −0
Original line number Diff line number Diff line
@@ -118,6 +118,9 @@ struct drm_i915_gem_object { 


	I915_SELFTEST_DECLARE(struct list_head st_link);



	unsigned long flags;

#define I915_BO_WAS_BOUND_BIT    0



	/*

	 * Is the object to be mapped as read-only to the GPU

	 * Only honoured if hardware has relevant pte bit

drivers/gpu/drm/i915/gem/i915_gem_pages.c

+10 −0
Original line number Diff line number Diff line
@@ -8,6 +8,8 @@ 
#include "i915_gem_object.h"

#include "i915_scatterlist.h"



#include "gt/intel_gt.h"



void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,

				 struct sg_table *pages,

				 unsigned int sg_page_sizes)
@@ -176,6 +178,14 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object *obj) 
	__i915_gem_object_reset_page_iter(obj);

	obj->mm.page_sizes.phys = obj->mm.page_sizes.sg = 0;



	if (test_and_clear_bit(I915_BO_WAS_BOUND_BIT, &obj->flags)) {

		struct drm_i915_private *i915 = to_i915(obj->base.dev);

		intel_wakeref_t wakeref;



		with_intel_runtime_pm_if_in_use(&i915->runtime_pm, wakeref)

			intel_gt_invalidate_tlbs(&i915->gt);

	}



	return pages;

}

drivers/gpu/drm/i915/gt/intel_gt.c

+99 −0
Original line number Diff line number Diff line
@@ -15,6 +15,8 @@ void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915) 


	spin_lock_init(&gt->irq_lock);



	mutex_init(&gt->tlb_invalidate_lock);



	INIT_LIST_HEAD(&gt->closed_vma);

	spin_lock_init(&gt->closed_lock);
@@ -266,3 +268,100 @@ void intel_gt_driver_late_release(struct intel_gt *gt) 
	intel_uc_driver_late_release(&gt->uc);

	intel_gt_fini_reset(gt);

}



struct reg_and_bit {

	i915_reg_t reg;

	u32 bit;

};



static struct reg_and_bit

get_reg_and_bit(const struct intel_engine_cs *engine, const bool gen8,

		const i915_reg_t *regs, const unsigned int num)

{

	const unsigned int class = engine->class;

	struct reg_and_bit rb = { };



	if (WARN_ON_ONCE(class >= num || !regs[class].reg))

		return rb;



	rb.reg = regs[class];

	if (gen8 && class == VIDEO_DECODE_CLASS)

		rb.reg.reg += 4 * engine->instance; /* GEN8_M2TCR */

	else

		rb.bit = engine->instance;



	rb.bit = BIT(rb.bit);



	return rb;

}



void intel_gt_invalidate_tlbs(struct intel_gt *gt)

{

	static const i915_reg_t gen8_regs[] = {

		[RENDER_CLASS]			= GEN8_RTCR,

		[VIDEO_DECODE_CLASS]		= GEN8_M1TCR, /* , GEN8_M2TCR */

		[VIDEO_ENHANCEMENT_CLASS]	= GEN8_VTCR,

		[COPY_ENGINE_CLASS]		= GEN8_BTCR,

	};

	static const i915_reg_t gen12_regs[] = {

		[RENDER_CLASS]			= GEN12_GFX_TLB_INV_CR,

		[VIDEO_DECODE_CLASS]		= GEN12_VD_TLB_INV_CR,

		[VIDEO_ENHANCEMENT_CLASS]	= GEN12_VE_TLB_INV_CR,

		[COPY_ENGINE_CLASS]		= GEN12_BLT_TLB_INV_CR,

	};

	struct drm_i915_private *i915 = gt->i915;

	struct intel_uncore *uncore = gt->uncore;

	struct intel_engine_cs *engine;

	enum intel_engine_id id;

	const i915_reg_t *regs;

	unsigned int num = 0;



	if (I915_SELFTEST_ONLY(gt->awake == -ENODEV))

		return;



	if (INTEL_GEN(i915) == 12) {

		regs = gen12_regs;

		num = ARRAY_SIZE(gen12_regs);

	} else if (INTEL_GEN(i915) >= 8 && INTEL_GEN(i915) <= 11) {

		regs = gen8_regs;

		num = ARRAY_SIZE(gen8_regs);

	} else if (INTEL_GEN(i915) < 8) {

		return;

	}



	if (WARN_ONCE(!num, "Platform does not implement TLB invalidation!"))

		return;



	GEM_TRACE("\n");



	assert_rpm_wakelock_held(&i915->runtime_pm);



	mutex_lock(&gt->tlb_invalidate_lock);

	intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);



	for_each_engine(engine, gt, id) {

		/*

		 * HW architecture suggest typical invalidation time at 40us,

		 * with pessimistic cases up to 100us and a recommendation to

		 * cap at 1ms. We go a bit higher just in case.

		 */

		const unsigned int timeout_us = 100;

		const unsigned int timeout_ms = 4;

		struct reg_and_bit rb;



		rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num);

		if (!i915_mmio_reg_offset(rb.reg))

			continue;



		intel_uncore_write_fw(uncore, rb.reg, rb.bit);

		if (__intel_wait_for_register_fw(uncore,

						 rb.reg, rb.bit, 0,

						 timeout_us, timeout_ms,

						 NULL))

			DRM_ERROR_RATELIMITED("%s TLB invalidation did not complete in %ums!\n",

					      engine->name, timeout_ms);

	}



	intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);

	mutex_unlock(&gt->tlb_invalidate_lock);

}