Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 96e821be authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman Committed by Alistair Delva
Browse files

Merge 5.2-rc7 into android-mainline 



Linux 5.2-rc7

Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@google.com>
parents d5458786 6fbc7275

Documentation/devicetree/bindings/riscv/cpus.yaml

+14 −12
Original line number Diff line number Diff line
@@ -152,6 +152,8 @@ examples: 
  - |

    // Example 2: Spike ISA Simulator with 1 Hart

    cpus {

        #address-cells = <1>;

        #size-cells = <0>;

        cpu@0 {

                device_type = "cpu";

                reg = <0>;

MAINTAINERS

+10 −0
Original line number Diff line number Diff line
@@ -3122,6 +3122,7 @@ F: arch/arm/mach-bcm/ 
BROADCOM BCM2835 ARM ARCHITECTURE

M:	Eric Anholt <eric@anholt.net>

M:	Stefan Wahren <wahrenst@gmx.net>

L:	bcm-kernel-feedback-list@broadcom.com

L:	linux-rpi-kernel@lists.infradead.org (moderated for non-subscribers)

L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

T:	git git://github.com/anholt/linux
@@ -3151,6 +3152,7 @@ F: arch/arm/boot/dts/bcm953012* 


BROADCOM BCM53573 ARM ARCHITECTURE

M:	Rafał Miłecki <rafal@milecki.pl>

L:	bcm-kernel-feedback-list@broadcom.com

L:	linux-arm-kernel@lists.infradead.org

S:	Maintained

F:	arch/arm/boot/dts/bcm53573*
@@ -3940,6 +3942,14 @@ M: Miguel Ojeda <miguel.ojeda.sandonis@gmail.com> 
S:	Maintained

F:	.clang-format



CLANG/LLVM BUILD SUPPORT

L:	clang-built-linux@googlegroups.com

W:	https://clangbuiltlinux.github.io/

B:	https://github.com/ClangBuiltLinux/linux/issues

C:	irc://chat.freenode.net/clangbuiltlinux

S:	Supported

K:	\b(?i:clang|llvm)\b



CLEANCACHE API

M:	Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>

L:	linux-kernel@vger.kernel.org

Makefile

+2 −2
Original line number Diff line number Diff line
@@ -2,8 +2,8 @@ 
VERSION = 5

PATCHLEVEL = 2

SUBLEVEL = 0

EXTRAVERSION = -rc6

NAME = Golden Lions

EXTRAVERSION = -rc7

NAME = Bobtail Squid



# *DOCUMENTATION*

# To see a list of typical targets execute "make help"

arch/arc/Makefile

+4 −0
Original line number Diff line number Diff line
@@ -5,6 +5,10 @@ 


KBUILD_DEFCONFIG := nsim_hs_defconfig



ifeq ($(CROSS_COMPILE),)

CROSS_COMPILE := $(call cc-cross-prefix, arc-linux- arceb-linux-)

endif



cflags-y	+= -fno-common -pipe -fno-builtin -mmedium-calls -D__linux__

cflags-$(CONFIG_ISA_ARCOMPACT)	+= -mA7

cflags-$(CONFIG_ISA_ARCV2)	+= -mcpu=hs38

arch/arc/plat-hsdk/platform.c

+153 −8
Original line number Diff line number Diff line
@@ -32,8 +32,6 @@ static void __init hsdk_init_per_cpu(unsigned int cpu) 


#define ARC_PERIPHERAL_BASE	0xf0000000

#define CREG_BASE		(ARC_PERIPHERAL_BASE + 0x1000)

#define CREG_PAE		(CREG_BASE + 0x180)

#define CREG_PAE_UPDATE		(CREG_BASE + 0x194)



#define SDIO_BASE		(ARC_PERIPHERAL_BASE + 0xA000)

#define SDIO_UHS_REG_EXT	(SDIO_BASE + 0x108)
@@ -99,20 +97,167 @@ static void __init hsdk_enable_gpio_intc_wire(void) 
	iowrite32(GPIO_INT_CONNECTED_MASK, (void __iomem *) GPIO_INTEN);

}



static void __init hsdk_init_early(void)

enum hsdk_axi_masters {

	M_HS_CORE = 0,

	M_HS_RTT,

	M_AXI_TUN,

	M_HDMI_VIDEO,

	M_HDMI_AUDIO,

	M_USB_HOST,

	M_ETHERNET,

	M_SDIO,

	M_GPU,

	M_DMAC_0,

	M_DMAC_1,

	M_DVFS

};



#define UPDATE_VAL	1



/*

 * This is modified configuration of AXI bridge. Default settings

 * are specified in "Table 111 CREG Address Decoder register reset values".

 *

 * AXI_M_m_SLV{0|1} - Slave Select register for master 'm'.

 * Possible slaves are:

 *  - 0  => no slave selected

 *  - 1  => DDR controller port #1

 *  - 2  => SRAM controller

 *  - 3  => AXI tunnel

 *  - 4  => EBI controller

 *  - 5  => ROM controller

 *  - 6  => AXI2APB bridge

 *  - 7  => DDR controller port #2

 *  - 8  => DDR controller port #3

 *  - 9  => HS38x4 IOC

 *  - 10 => HS38x4 DMI

 * AXI_M_m_OFFSET{0|1} - Addr Offset register for master 'm'

 *

 * Please read ARC HS Development IC Specification, section 17.2 for more

 * information about apertures configuration.

 *

 * m	master		AXI_M_m_SLV0	AXI_M_m_SLV1	AXI_M_m_OFFSET0	AXI_M_m_OFFSET1

 * 0	HS (CBU)	0x11111111	0x63111111	0xFEDCBA98	0x0E543210

 * 1	HS (RTT)	0x77777777	0x77777777	0xFEDCBA98	0x76543210

 * 2	AXI Tunnel	0x88888888	0x88888888	0xFEDCBA98	0x76543210

 * 3	HDMI-VIDEO	0x77777777	0x77777777	0xFEDCBA98	0x76543210

 * 4	HDMI-ADUIO	0x77777777	0x77777777	0xFEDCBA98	0x76543210

 * 5	USB-HOST	0x77777777	0x77999999	0xFEDCBA98	0x76DCBA98

 * 6	ETHERNET	0x77777777	0x77999999	0xFEDCBA98	0x76DCBA98

 * 7	SDIO		0x77777777	0x77999999	0xFEDCBA98	0x76DCBA98

 * 8	GPU		0x77777777	0x77777777	0xFEDCBA98	0x76543210

 * 9	DMAC (port #1)	0x77777777	0x77777777	0xFEDCBA98	0x76543210

 * 10	DMAC (port #2)	0x77777777	0x77777777	0xFEDCBA98	0x76543210

 * 11	DVFS		0x00000000	0x60000000	0x00000000	0x00000000

 */



#define CREG_AXI_M_SLV0(m)  ((void __iomem *)(CREG_BASE + 0x20 * (m)))

#define CREG_AXI_M_SLV1(m)  ((void __iomem *)(CREG_BASE + 0x20 * (m) + 0x04))

#define CREG_AXI_M_OFT0(m)  ((void __iomem *)(CREG_BASE + 0x20 * (m) + 0x08))

#define CREG_AXI_M_OFT1(m)  ((void __iomem *)(CREG_BASE + 0x20 * (m) + 0x0C))

#define CREG_AXI_M_UPDT(m)  ((void __iomem *)(CREG_BASE + 0x20 * (m) + 0x14))



#define CREG_AXI_M_HS_CORE_BOOT	((void __iomem *)(CREG_BASE + 0x010))



#define CREG_PAE		((void __iomem *)(CREG_BASE + 0x180))

#define CREG_PAE_UPDT		((void __iomem *)(CREG_BASE + 0x194))



static void __init hsdk_init_memory_bridge(void)

{

	u32 reg;



	/*

	 * M_HS_CORE has one unique register - BOOT.

	 * We need to clean boot mirror (BOOT[1:0]) bits in them to avoid first

	 * aperture to be masked by 'boot mirror'.

	 */

	reg = readl(CREG_AXI_M_HS_CORE_BOOT) & (~0x3);

	writel(reg, CREG_AXI_M_HS_CORE_BOOT);

	writel(0x11111111, CREG_AXI_M_SLV0(M_HS_CORE));

	writel(0x63111111, CREG_AXI_M_SLV1(M_HS_CORE));

	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_CORE));

	writel(0x0E543210, CREG_AXI_M_OFT1(M_HS_CORE));

	writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_CORE));



	writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT));

	writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT));

	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT));

	writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT));

	writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT));



	writel(0x88888888, CREG_AXI_M_SLV0(M_AXI_TUN));

	writel(0x88888888, CREG_AXI_M_SLV1(M_AXI_TUN));

	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_AXI_TUN));

	writel(0x76543210, CREG_AXI_M_OFT1(M_AXI_TUN));

	writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_AXI_TUN));



	writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_VIDEO));

	writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_VIDEO));

	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_VIDEO));

	writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_VIDEO));

	writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_VIDEO));



	writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_AUDIO));

	writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_AUDIO));

	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_AUDIO));

	writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_AUDIO));

	writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_AUDIO));



	writel(0x77777777, CREG_AXI_M_SLV0(M_USB_HOST));

	writel(0x77999999, CREG_AXI_M_SLV1(M_USB_HOST));

	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_USB_HOST));

	writel(0x76DCBA98, CREG_AXI_M_OFT1(M_USB_HOST));

	writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_USB_HOST));



	writel(0x77777777, CREG_AXI_M_SLV0(M_ETHERNET));

	writel(0x77999999, CREG_AXI_M_SLV1(M_ETHERNET));

	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_ETHERNET));

	writel(0x76DCBA98, CREG_AXI_M_OFT1(M_ETHERNET));

	writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_ETHERNET));



	writel(0x77777777, CREG_AXI_M_SLV0(M_SDIO));

	writel(0x77999999, CREG_AXI_M_SLV1(M_SDIO));

	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_SDIO));

	writel(0x76DCBA98, CREG_AXI_M_OFT1(M_SDIO));

	writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_SDIO));



	writel(0x77777777, CREG_AXI_M_SLV0(M_GPU));

	writel(0x77777777, CREG_AXI_M_SLV1(M_GPU));

	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_GPU));

	writel(0x76543210, CREG_AXI_M_OFT1(M_GPU));

	writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_GPU));



	writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_0));

	writel(0x77777777, CREG_AXI_M_SLV1(M_DMAC_0));

	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_0));

	writel(0x76543210, CREG_AXI_M_OFT1(M_DMAC_0));

	writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_0));



	writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_1));

	writel(0x77777777, CREG_AXI_M_SLV1(M_DMAC_1));

	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_1));

	writel(0x76543210, CREG_AXI_M_OFT1(M_DMAC_1));

	writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_1));



	writel(0x00000000, CREG_AXI_M_SLV0(M_DVFS));

	writel(0x60000000, CREG_AXI_M_SLV1(M_DVFS));

	writel(0x00000000, CREG_AXI_M_OFT0(M_DVFS));

	writel(0x00000000, CREG_AXI_M_OFT1(M_DVFS));

	writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DVFS));



	/*

	 * PAE remapping for DMA clients does not work due to an RTL bug, so

	 * CREG_PAE register must be programmed to all zeroes, otherwise it

	 * will cause problems with DMA to/from peripherals even if PAE40 is

	 * not used.

	 */

	writel(0x00000000, CREG_PAE);

	writel(UPDATE_VAL, CREG_PAE_UPDT);

}



	/* Default is 1, which means "PAE offset = 4GByte" */

	writel_relaxed(0, (void __iomem *) CREG_PAE);



	/* Really apply settings made above */

	writel(1, (void __iomem *) CREG_PAE_UPDATE);

static void __init hsdk_init_early(void)

{

	hsdk_init_memory_bridge();



	/*

	 * Switch SDIO external ciu clock divider from default div-by-8 to