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Commit 96c55900 authored by Myron Stowe's avatar Myron Stowe Committed by Jesse Barnes
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PCI: Pull PCI 'latency timer' setup up into the core 



The 'latency timer' of PCI devices, both Type 0 and Type 1,
is setup in architecture-specific code [see: 'pcibios_set_master()'].
There are two approaches being taken by all the architectures - check
if the 'latency timer' is currently set between 16 and 255 and if not
bring it within bounds, or, do nothing (and then there is the
gratuitously different PA-RISC implementation).

There is nothing architecture-specific about PCI's 'latency timer' so
this patch pulls its setup functionality up into the PCI core by
creating a generic 'pcibios_set_master()' function using the '__weak'
attribute which can be used by all architectures as a default which,
if necessary, can then be over-ridden by architecture-specific code.

No functional change.

Signed-off-by: default avatarMyron Stowe <myron.stowe@redhat.com>
Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
parent 9cdce18d

arch/blackfin/include/asm/pci.h

+0 −4
Original line number Diff line number Diff line
@@ -10,10 +10,6 @@ 
#define PCIBIOS_MIN_IO 0x00001000

#define PCIBIOS_MIN_MEM 0x10000000



static inline void pcibios_set_master(struct pci_dev *dev)

{

	/* No special bus mastering setup handling */

}

static inline void pcibios_penalize_isa_irq(int irq)

{

	/* We don't do dynamic PCI IRQ allocation */

arch/frv/mb93090-mb00/pci-frv.c

+0 −6
Original line number Diff line number Diff line
@@ -195,12 +195,6 @@ void __init pcibios_resource_survey(void) 
	pcibios_assign_resources();

}



/*

 *  If we set up a device for bus mastering, we need to check the latency

 *  timer as certain crappy BIOSes forget to set it properly.

 */

unsigned int pcibios_max_latency = 255;



void pcibios_set_master(struct pci_dev *dev)

{

	u8 lat;

arch/frv/mb93090-mb00/pci-frv.h

+0 −2
Original line number Diff line number Diff line
@@ -26,8 +26,6 @@ extern unsigned int __nongpreldata pci_probe; 


/* pci-frv.c */



extern unsigned int pcibios_max_latency;



void pcibios_resource_survey(void);



/* pci-vdk.c */

arch/h8300/include/asm/pci.h

+0 −5
Original line number Diff line number Diff line
@@ -9,11 +9,6 @@ 


#define pcibios_assign_all_busses()	0



static inline void pcibios_set_master(struct pci_dev *dev)

{

	/* No special bus mastering setup handling */

}



static inline void pcibios_penalize_isa_irq(int irq, int active)

{

	/* We don't do dynamic PCI IRQ allocation */

arch/mips/pci/pci.c

+0 −6
Original line number Diff line number Diff line
@@ -205,12 +205,6 @@ static int pcibios_enable_resources(struct pci_dev *dev, int mask) 
	return 0;

}



/*

 *  If we set up a device for bus mastering, we need to check the latency

 *  timer as certain crappy BIOSes forget to set it properly.

 */

static unsigned int pcibios_max_latency = 255;



void pcibios_set_master(struct pci_dev *dev)

{

	u8 lat;