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Commit 96b7dfb7 authored by Satheeshakrishna M's avatar Satheeshakrishna M Committed by Daniel Vetter
Browse files

drm/i915/skl: Query DPLL attached to port on SKL 



Modify the implementation to query DPLL attached to a SKL port.

v2: Rebase on top of the run-time PM on DPMS series (Damien)

v3: Modified as per review comments from Paulo

Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarSatheeshakrishna M <satheeshakrishna.m@intel.com>
Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 540e732c

drivers/gpu/drm/i915/intel_display.c

+28 −1
Original line number Diff line number Diff line
@@ -7960,6 +7960,30 @@ static int haswell_crtc_compute_clock(struct intel_crtc *crtc) 
	return 0;

}



static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,

				enum port port,

				struct intel_crtc_config *pipe_config)

{

	u32 temp;



	temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);

	pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);



	switch (pipe_config->ddi_pll_sel) {

	case SKL_DPLL1:

		pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;

		break;

	case SKL_DPLL2:

		pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;

		break;

	case SKL_DPLL3:

		pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;

		break;

	default:

		WARN(1, "Unknown DPLL programmed\n");

	}

}



static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,

				enum port port,

				struct intel_crtc_config *pipe_config)
@@ -7989,6 +8013,9 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc, 


	port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;



	if (IS_SKYLAKE(dev))

		skylake_get_ddi_pll(dev_priv, port, pipe_config);

	else

		haswell_get_ddi_pll(dev_priv, port, pipe_config);



	if (pipe_config->shared_dpll >= 0) {

drivers/gpu/drm/i915/intel_drv.h

+4 −1
Original line number Diff line number Diff line
@@ -343,7 +343,10 @@ struct intel_crtc_config { 
	/* Selected dpll when shared or DPLL_ID_PRIVATE. */

	enum intel_dpll_id shared_dpll;



	/* PORT_CLK_SEL for DDI ports. */

	/*

	 * - PORT_CLK_SEL for DDI ports on HSW/BDW.

	 * - enum skl_dpll on SKL

	 */

	uint32_t ddi_pll_sel;



	/* Actual register state of the dpll, for shared dpll cross-checking. */