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Commit 96a16069 authored by Mario Limonciello's avatar Mario Limonciello Committed by Greg Kroah-Hartman
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pinctrl: amd: Only use special debounce behavior for GPIO 0 



commit 0d5ace1a07f7e846d0f6d972af60d05515599d0b upstream.

It's uncommon to use debounce on any other pin, but technically
we should only set debounce to 0 when working off GPIO0.

Cc: stable@vger.kernel.org
Tested-by: default avatarJan Visser <starquake@linuxeverywhere.org>
Fixes: 968ab9261627 ("pinctrl: amd: Detect internal GPIO0 debounce handling")
Signed-off-by: default avatarMario Limonciello <mario.limonciello@amd.com>
Link: https://lore.kernel.org/r/20230705133005.577-2-mario.limonciello@amd.com


Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 6dcb493f

drivers/pinctrl/pinctrl-amd.c

+5 −3
Original line number Diff line number Diff line
@@ -125,9 +125,11 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, 
	raw_spin_lock_irqsave(&gpio_dev->lock, flags);



	/* Use special handling for Pin0 debounce */

	if (offset == 0) {

		pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);

		if (pin_reg & INTERNAL_GPIO0_DEBOUNCE)

			debounce = 0;

	}



	pin_reg = readl(gpio_dev->base + offset * 4);