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Commit 965ebe3d authored by Michel Dänzer's avatar Michel Dänzer Committed by Alex Deucher
Browse files

drm/amdgpu: Update pitch on page flips without DC as well 



DC already handles this correctly since amdgpu minor version 31. Bump
the minor version again so that xf86-video-amdgpu can take advantage of
this working without DC as well now.

Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarMichel Dänzer <michel.daenzer@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 29c9d8ea

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+2 −1
Original line number Diff line number Diff line
@@ -79,9 +79,10 @@ 
 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC

 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.

 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.

 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches

 */

#define KMS_DRIVER_MAJOR	3

#define KMS_DRIVER_MINOR	33

#define KMS_DRIVER_MINOR	34

#define KMS_DRIVER_PATCHLEVEL	0



#define AMDGPU_MAX_TIMEOUT_PARAM_LENTH	256

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

+4 −0
Original line number Diff line number Diff line
@@ -236,6 +236,7 @@ static void dce_v10_0_page_flip(struct amdgpu_device *adev, 
				int crtc_id, u64 crtc_base, bool async)

{

	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];

	struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;

	u32 tmp;



	/* flip at hsync for async, default is vsync */
@@ -243,6 +244,9 @@ static void dce_v10_0_page_flip(struct amdgpu_device *adev, 
	tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,

			    GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);

	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);

	/* update pitch */

	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,

	       fb->pitches[0] / fb->format->cpp[0]);

	/* update the primary scanout address */

	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,

	       upper_32_bits(crtc_base));

drivers/gpu/drm/amd/amdgpu/dce_v11_0.c

+4 −0
Original line number Diff line number Diff line
@@ -254,6 +254,7 @@ static void dce_v11_0_page_flip(struct amdgpu_device *adev, 
				int crtc_id, u64 crtc_base, bool async)

{

	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];

	struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;

	u32 tmp;



	/* flip immediate for async, default is vsync */
@@ -261,6 +262,9 @@ static void dce_v11_0_page_flip(struct amdgpu_device *adev, 
	tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,

			    GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0);

	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);

	/* update pitch */

	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,

	       fb->pitches[0] / fb->format->cpp[0]);

	/* update the scanout addresses */

	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,

	       upper_32_bits(crtc_base));

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

+4 −0
Original line number Diff line number Diff line
@@ -191,10 +191,14 @@ static void dce_v6_0_page_flip(struct amdgpu_device *adev, 
			       int crtc_id, u64 crtc_base, bool async)

{

	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];

	struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;



	/* flip at hsync for async, default is vsync */

	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?

	       GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);

	/* update pitch */

	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,

	       fb->pitches[0] / fb->format->cpp[0]);

	/* update the scanout addresses */

	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,

	       upper_32_bits(crtc_base));

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

+4 −0
Original line number Diff line number Diff line
@@ -184,10 +184,14 @@ static void dce_v8_0_page_flip(struct amdgpu_device *adev, 
			       int crtc_id, u64 crtc_base, bool async)

{

	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];

	struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;



	/* flip at hsync for async, default is vsync */

	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?

	       GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);

	/* update pitch */

	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,

	       fb->pitches[0] / fb->format->cpp[0]);

	/* update the primary scanout addresses */

	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,

	       upper_32_bits(crtc_base));