dt-bindings: fpga: Add bindings document for Xilinx LogiCore PR Decoupler

Xilinx LogiCORE Partial Reconfig Decoupler Softcore

The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more

decouplers / fpga bridges.

The controller can decouple/disable the bridges which prevents signal

changes from passing through the bridge.  The controller can also

couple / enable the bridges which allows traffic to pass through the

bridge normally.

The Driver supports only MMIO handling. A PR region can have multiple

PR Decouplers which can be handled independently or chained via decouple/

decouple_status signals.

Required properties:

- compatible		: Should contain "xlnx,pr-decoupler-1.00" followed by

                          "xlnx,pr-decoupler"

- regs			: base address and size for decoupler module

- clocks		: input clock to IP

- clock-names		: should contain "aclk"

Optional properties:

- bridge-enable		: 0 if driver should disable bridge at startup

			  1 if driver should enable bridge at startup

			  Default is to leave bridge in current state.

See Documentation/devicetree/bindings/fpga/fpga-region.txt for generic bindings.

Example:

	fpga-bridge@100000450 {

		compatible = "xlnx,pr-decoupler-1.00",

			     "xlnx-pr-decoupler";

		regs = <0x10000045 0x10>;

		clocks = <&clkc 15>;

		clock-names = "aclk";

		bridge-enable = <0>;

	};