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Commit 960e5465 authored by Sagar Arun Kamble's avatar Sagar Arun Kamble Committed by Chris Wilson
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drm/i915: Separate RPS and RC6 handling for gen6+ 



This patch separates enable/disable of RC6 and RPS for gen6+
platforms prior to VLV.

v2: Fixed checkpatch issue. (Sagar)

Signed-off-by: default avatarSagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com> #1
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/1507360055-19948-2-git-send-email-sagar.a.kamble@intel.com


Acked-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20171010213010.7415-1-chris@chris-wilson.co.uk
parent 617dc761

drivers/gpu/drm/i915/i915_debugfs.c

+8 −9
Original line number Diff line number Diff line
@@ -1190,6 +1190,13 @@ static int i915_frequency_info(struct seq_file *m, void *unused) 
			pm_iir = I915_READ(GEN8_GT_IIR(2));

			pm_mask = I915_READ(GEN6_PMINTRMSK);

		}

		seq_printf(m, "Video Turbo Mode: %s\n",

			   yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));

		seq_printf(m, "HW control enabled: %s\n",

			   yesno(rpmodectl & GEN6_RP_ENABLE));

		seq_printf(m, "SW control enabled: %s\n",

			   yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==

				  GEN6_RP_MEDIA_SW_MODE));

		seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",

			   pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);

		seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
@@ -1533,7 +1540,7 @@ static int vlv_drpc_info(struct seq_file *m) 
static int gen6_drpc_info(struct seq_file *m)

{

	struct drm_i915_private *dev_priv = node_to_i915(m->private);

	u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;

	u32 gt_core_status, rcctl1, rc6vids = 0;

	u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;

	unsigned forcewake_count;

	int count = 0;
@@ -1552,7 +1559,6 @@ static int gen6_drpc_info(struct seq_file *m) 
	gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);

	trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);



	rpmodectl1 = I915_READ(GEN6_RP_CONTROL);

	rcctl1 = I915_READ(GEN6_RC_CONTROL);

	if (INTEL_GEN(dev_priv) >= 9) {

		gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
@@ -1563,13 +1569,6 @@ static int gen6_drpc_info(struct seq_file *m) 
	sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);

	mutex_unlock(&dev_priv->rps.hw_lock);



	seq_printf(m, "Video Turbo Mode: %s\n",

		   yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));

	seq_printf(m, "HW control enabled: %s\n",

		   yesno(rpmodectl1 & GEN6_RP_ENABLE));

	seq_printf(m, "SW control enabled: %s\n",

		   yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==

			  GEN6_RP_MEDIA_SW_MODE));

	seq_printf(m, "RC1e Enabled: %s\n",

		   yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));

	seq_printf(m, "RC6 Enabled: %s\n",

drivers/gpu/drm/i915/intel_pm.c

+29 −14
Original line number Diff line number Diff line
@@ -6334,9 +6334,13 @@ static void gen9_disable_rps(struct drm_i915_private *dev_priv) 
	I915_WRITE(GEN6_RP_CONTROL, 0);

}



static void gen6_disable_rps(struct drm_i915_private *dev_priv)

static void gen6_disable_rc6(struct drm_i915_private *dev_priv)

{

	I915_WRITE(GEN6_RC_CONTROL, 0);

}



static void gen6_disable_rps(struct drm_i915_private *dev_priv)

{

	I915_WRITE(GEN6_RPNSWREQ, 1 << 31);

	I915_WRITE(GEN6_RP_CONTROL, 0);

}
@@ -6694,7 +6698,7 @@ static void gen8_enable_rps(struct drm_i915_private *dev_priv) 
	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);

}



static void gen6_enable_rps(struct drm_i915_private *dev_priv)

static void gen6_enable_rc6(struct drm_i915_private *dev_priv)

{

	struct intel_engine_cs *engine;

	enum intel_engine_id id;
@@ -6705,12 +6709,6 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv) 


	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));



	/* Here begins a magic sequence of register writes to enable

	 * auto-downclocking.

	 *

	 * Perhaps there might be some value in exposing these to

	 * userspace...

	 */

	I915_WRITE(GEN6_RC_STATE, 0);



	/* Clear the DBG now so we don't confuse earlier errors */
@@ -6764,12 +6762,6 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv) 
		   GEN6_RC_CTL_EI_MODE(1) |

		   GEN6_RC_CTL_HW_ENABLE);



	/* Power down if completely idle for over 50ms */

	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);

	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);



	reset_rps(dev_priv, gen6_set_rps);



	rc6vids = 0;

	ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);

	if (IS_GEN6(dev_priv) && ret) {
@@ -6787,6 +6779,27 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv) 
	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);

}



static void gen6_enable_rps(struct drm_i915_private *dev_priv)

{

	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));



	/* Here begins a magic sequence of register writes to enable

	 * auto-downclocking.

	 *

	 * Perhaps there might be some value in exposing these to

	 * userspace...

	 */

	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);



	/* Power down if completely idle for over 50ms */

	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);

	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);



	reset_rps(dev_priv, gen6_set_rps);



	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);

}



static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)

{

	int min_freq = 15;
@@ -7936,6 +7949,7 @@ void intel_disable_gt_powersave(struct drm_i915_private *dev_priv) 
	} else if (IS_VALLEYVIEW(dev_priv)) {

		valleyview_disable_rps(dev_priv);

	} else if (INTEL_GEN(dev_priv) >= 6) {

		gen6_disable_rc6(dev_priv);

		gen6_disable_rps(dev_priv);

	}  else if (IS_IRONLAKE_M(dev_priv)) {

		ironlake_disable_drps(dev_priv);
@@ -7972,6 +7986,7 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv) 
		gen8_enable_rps(dev_priv);

		gen6_update_ring_freq(dev_priv);

	} else if (INTEL_GEN(dev_priv) >= 6) {

		gen6_enable_rc6(dev_priv);

		gen6_enable_rps(dev_priv);

		gen6_update_ring_freq(dev_priv);

	} else if (IS_IRONLAKE_M(dev_priv)) {