Loading bindings/media/msm-cvp.txt 0 → 100644 +152 −0 Original line number Diff line number Diff line * Qualcomm Technologies, Inc. MSM CVP [Root level node] cvp ===== Required properties: - compatible : one of: - "qcom,msm-cvp" - "qcom,lahaina-cvp" : Invokes driver specific data for Lahaina. Optional properties: - reg : offset and length of the CSR register set for the device. - interrupts : should contain the cvp interrupt. - qcom,reg-presets : list of offset-value pairs for registers to be written. The offsets are from the base offset specified in 'reg'. This is mainly used for QoS, VBIF, etc. presets for video. - qcom,qdss-presets : list of physical address and memory allocation size pairs. when fw_debug_mode is set as HFI_DEBUG_MODE_QDSS, all firmware messages will be written to QDSS memory. - *-supply: A phandle pointing to the appropriate regulator. Number of regulators vary across targets. - clock-names: an array of clocks that the driver is supposed to be manipulating. The clocks names here correspond to the clock names used in clk_get(<name>). - qcom,clock-configs = an array of bitmaps of clocks' configurations. The index of the bitmap corresponds to the clock at the same index in qcom,clock-names. The bitmaps describes the actions that the device needs to take regarding the clock (i.e. scale it based on load). The bitmap is defined as: scalable = 0x1 (if the driver should vary the clock's frequency based on load) - qcom,allowed-clock-rates = an array of supported clock rates by the chipset. - qcom,use-non-secure-pil = A bool indicating which type of pil to use to load the fw. - qcom,fw-bias = The address at which cvp fw is loaded (manually). [Second level nodes] Context Banks ============= Required properties: - compatible : one of: - "qcom,msm-cvp,context-bank" - iommus : A phandle parsed by smmu driver. Number of entries will vary across targets. Optional properties: - label - string describing iommu domain usage. - buffer-types : bitmap of buffer types that can be mapped into the current IOMMU domain. - Buffer types are defined as the following: input = 0x1 output = 0x2 output2 = 0x4 extradata input = 0x8 extradata output = 0x10 extradata output2 = 0x20 internal scratch = 0x40 internal scratch1 = 0x80 internal scratch2 = 0x100 internal persist = 0x200 internal persist1 = 0x400 internal cmd queue = 0x800 - virtual-addr-pool : offset and length of virtual address pool. - qcom,fw-context-bank : bool indicating firmware context bank. - qcom,secure-context-bank : bool indicating secure context bank. Buses ===== Required properties: - compatible : one of: - "qcom,msm-cvp,bus" - label : an arbitrary name - qcom,bus-master : an integer descriptor of the bus master. Refer to arch/arm/\ boot/dts/include/dt-bindings/msm/msm-bus-ids.h for list of acceptable masters - qcom,bus-slave : an integer descriptor of the bus slave. Refer to arch/arm/\ boot/dts/include/dt-bindings/msm/msm-bus-ids.h for list of acceptable slaves Optional properties: - qcom,bus-governor : governor to use when scaling bus, generally any commonly found devfreq governor might be used. In addition to those governors, the custom Venus governors, "msm-vidc-ddr" or "msm-vidc-llcc" are also acceptable values. In the absence of this property the "performance" governor is used. - qcom,bus-rage-kbps : an array of two items (<min max>) that indicate the minimum and maximum acceptable votes for the bus. In the absence of this property <0 INT_MAX> is used. - qcom,ubwc-10bit : UBWC 10 bit content has different bus requirements, this tag will be used to pick the appropriate bus as per the session profile as shown below in example. Memory Heaps ============ Required properties: - compatible : one of: - "qcom,msm-vidc,mem-cdsp" - memory-region : phandle to the memory heap/region. Example: msm_cvp: qcom,cvp@ab00000 { compatible = "qcom,msm-cvp", "qcom,Lahaina-cvp"; status = "ok"; reg = <0xab00000 0x100000>; interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; /* FIXME: LLCC Info */ /* cache-slice-names = "vidsc0", "vidsc1"; */ /* cache-slices = <&llcc 2>, <&llcc 3>; */ /* Supply */ cvp-supply = <&mvs1_gdsc>; /* Clocks */ clock-names = "gcc_video_axi0", "gcc_video_axi1", "cvp_clk"; clocks = <&clock_gcc GCC_VIDEO_AXI0_CLK>, <&clock_gcc GCC_VIDEO_AXI1_CLK>, <&clock_videocc VIDEO_CC_MVS1_CLK>; qcom,proxy-clock-names = "gcc_video_axi0", "gcc_video_axi1", "cvp_clk"; qcom,clock-configs = <0x0 0x0 0x1>; qcom,allowed-clock-rates = <403000000 520000000 549000000 666000000 800000000>; /* Buses */ bus_cnoc { compatible = "qcom,msm-cvp,bus"; label = "cnoc"; qcom,bus-master = <MSM_BUS_MASTER_AMPSS_M0>; qcom,bus-slave = <MSM_BUS_SLAVE_VENUS_CFG>; qcom,bus-governor = "performance"; qcom,bus-range-kbps = <1000 1000>; }; /* MMUs */ non_secure_cb { compatible = "qcom,msm-cvp,context-bank"; label = "cvp_hlos"; iommus = <&apps_smmu 0x2120 0x400>; qcom,iommu-dma = "disabled"; buffer-types = <0xfff>; virtual-addr-pool = <0x4b000000 0xe0000000>; }; /* Memory Heaps */ qcom,msm-cvp,mem_cdsp { compatible = "qcom,msm-cvp,mem-cdsp"; memory-region = <&cdsp_mem>; }; }; qcom/lahaina-cvp.dtsi 0 → 100644 +92 −0 Original line number Diff line number Diff line #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/soc/qcom,ipcc.h> #include <dt-bindings/interconnect/qcom,lahaina.h> #include <dt-bindings/clock/qcom,videocc-lahaina.h> &soc { msm_cvp: qcom,cvp@ab00000 { compatible = "qcom,msm-cvp", "qcom,lahaina-cvp"; status = "ok"; reg = <0xab00000 0x100000>; interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; /* LLCC Cache */ cache-slice-names = "cvp"; /* Supply */ cvp-supply = <&video_cc_mvs1c_gdsc>; cvp-core-supply = <&video_cc_mvs1_gdsc>; /* Clocks */ clock-names = "gcc_video_axi1", "cvp_clk", "core_clk"; clocks = <&clock_gcc GCC_VIDEO_AXI1_CLK>, <&clock_videocc VIDEO_CC_MVS1C_CLK>, <&clock_videocc VIDEO_CC_MVS1_CLK>; qcom,proxy-clock-names = "gcc_video_axi1", "cvp_clk", "core_clk"; qcom,clock-configs = <0x0 0x1 0x1>; qcom,allowed-clock-rates = <280000000 366000000 444000000>; resets = <&clock_videocc VIDEO_CC_MVS1C_CLK_ARES>; reset-names = "cvp_core_reset"; qcom,reg-presets = <0xB0088 0x0>; /* Buses */ cvp_cnoc { compatible = "qcom,msm-cvp,bus"; label = "cvp-cnoc"; qcom,bus-master = <MASTER_APPSS_PROC>; qcom,bus-slave = <SLAVE_VENUS_CFG>; qcom,bus-governor = "performance"; qcom,bus-range-kbps = <1000 1000>; }; cvp_bus_ddr { compatible = "qcom,msm-cvp,bus"; label = "cvp-ddr"; qcom,bus-master = <MASTER_VIDEO_PROC>; qcom,bus-slave = <SLAVE_EBI1>; qcom,bus-governor = "performance"; qcom,bus-range-kbps = <1000 6533000>; }; /* MMUs */ cvp_non_secure_cb { compatible = "qcom,msm-cvp,context-bank"; label = "cvp_hlos"; iommus = <&apps_smmu 0x2120 0x400>; buffer-types = <0xfff>; qcom,iommu-dma-addr-pool = <0x4b000000 0x90000000>; }; cvp_secure_nonpixel_cb { compatible = "qcom,msm-cvp,context-bank"; label = "cvp_sec_nonpixel"; iommus = <&apps_smmu 0x2124 0x400>; buffer-types = <0x741>; qcom,iommu-dma-addr-pool = <0x01000000 0x25800000>; qcom,iommu-vmid = <0xB>; }; cvp_secure_pixel_cb { compatible = "qcom,msm-cvp,context-bank"; label = "cvp_sec_pixel"; iommus = <&apps_smmu 0x2123 0x400>; buffer-types = <0x106>; qcom,iommu-dma-addr-pool = <0x26800000 0x24800000>; qcom,iommu-vmid = <0xA>; }; /* Memory Heaps */ qcom,msm-cvp,mem_cdsp { compatible = "qcom,msm-cvp,mem-cdsp"; memory-region = <&cdsp_mem>; }; }; }; qcom/lahaina.dtsi +19 −0 Original line number Diff line number Diff line Loading @@ -339,6 +339,15 @@ size = <0x0 0x800000>; }; cdsp_mem: cdsp_region { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; reusable; alignment = <0x0 0x400000>; size = <0x0 0x400000>; }; cdsp_secure_heap: cdsp_secure_heap@9b200000 { reg = <0x0 0x9b200000 0x0 0x4600000>; }; Loading Loading @@ -1683,6 +1692,15 @@ qcom,iommu-group = <>; }; }; qcom,cvpss@abb0000 { compatible = "qcom,pil-tz-generic"; reg = <0xabb0000 0x2000>; status = "ok"; qcom,pas-id = <26>; qcom,firmware-name = "cvpss"; memory-region = <&pil_cvp_mem>; }; }; #include "lahaina-regulators.dtsi" Loading @@ -1694,3 +1712,4 @@ #include "lahaina-pm.dtsi" #include "lahaina-qupv3.dtsi" #include "lahaina-vidc.dtsi" #include "lahaina-cvp.dtsi" Loading
bindings/media/msm-cvp.txt 0 → 100644 +152 −0 Original line number Diff line number Diff line * Qualcomm Technologies, Inc. MSM CVP [Root level node] cvp ===== Required properties: - compatible : one of: - "qcom,msm-cvp" - "qcom,lahaina-cvp" : Invokes driver specific data for Lahaina. Optional properties: - reg : offset and length of the CSR register set for the device. - interrupts : should contain the cvp interrupt. - qcom,reg-presets : list of offset-value pairs for registers to be written. The offsets are from the base offset specified in 'reg'. This is mainly used for QoS, VBIF, etc. presets for video. - qcom,qdss-presets : list of physical address and memory allocation size pairs. when fw_debug_mode is set as HFI_DEBUG_MODE_QDSS, all firmware messages will be written to QDSS memory. - *-supply: A phandle pointing to the appropriate regulator. Number of regulators vary across targets. - clock-names: an array of clocks that the driver is supposed to be manipulating. The clocks names here correspond to the clock names used in clk_get(<name>). - qcom,clock-configs = an array of bitmaps of clocks' configurations. The index of the bitmap corresponds to the clock at the same index in qcom,clock-names. The bitmaps describes the actions that the device needs to take regarding the clock (i.e. scale it based on load). The bitmap is defined as: scalable = 0x1 (if the driver should vary the clock's frequency based on load) - qcom,allowed-clock-rates = an array of supported clock rates by the chipset. - qcom,use-non-secure-pil = A bool indicating which type of pil to use to load the fw. - qcom,fw-bias = The address at which cvp fw is loaded (manually). [Second level nodes] Context Banks ============= Required properties: - compatible : one of: - "qcom,msm-cvp,context-bank" - iommus : A phandle parsed by smmu driver. Number of entries will vary across targets. Optional properties: - label - string describing iommu domain usage. - buffer-types : bitmap of buffer types that can be mapped into the current IOMMU domain. - Buffer types are defined as the following: input = 0x1 output = 0x2 output2 = 0x4 extradata input = 0x8 extradata output = 0x10 extradata output2 = 0x20 internal scratch = 0x40 internal scratch1 = 0x80 internal scratch2 = 0x100 internal persist = 0x200 internal persist1 = 0x400 internal cmd queue = 0x800 - virtual-addr-pool : offset and length of virtual address pool. - qcom,fw-context-bank : bool indicating firmware context bank. - qcom,secure-context-bank : bool indicating secure context bank. Buses ===== Required properties: - compatible : one of: - "qcom,msm-cvp,bus" - label : an arbitrary name - qcom,bus-master : an integer descriptor of the bus master. Refer to arch/arm/\ boot/dts/include/dt-bindings/msm/msm-bus-ids.h for list of acceptable masters - qcom,bus-slave : an integer descriptor of the bus slave. Refer to arch/arm/\ boot/dts/include/dt-bindings/msm/msm-bus-ids.h for list of acceptable slaves Optional properties: - qcom,bus-governor : governor to use when scaling bus, generally any commonly found devfreq governor might be used. In addition to those governors, the custom Venus governors, "msm-vidc-ddr" or "msm-vidc-llcc" are also acceptable values. In the absence of this property the "performance" governor is used. - qcom,bus-rage-kbps : an array of two items (<min max>) that indicate the minimum and maximum acceptable votes for the bus. In the absence of this property <0 INT_MAX> is used. - qcom,ubwc-10bit : UBWC 10 bit content has different bus requirements, this tag will be used to pick the appropriate bus as per the session profile as shown below in example. Memory Heaps ============ Required properties: - compatible : one of: - "qcom,msm-vidc,mem-cdsp" - memory-region : phandle to the memory heap/region. Example: msm_cvp: qcom,cvp@ab00000 { compatible = "qcom,msm-cvp", "qcom,Lahaina-cvp"; status = "ok"; reg = <0xab00000 0x100000>; interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; /* FIXME: LLCC Info */ /* cache-slice-names = "vidsc0", "vidsc1"; */ /* cache-slices = <&llcc 2>, <&llcc 3>; */ /* Supply */ cvp-supply = <&mvs1_gdsc>; /* Clocks */ clock-names = "gcc_video_axi0", "gcc_video_axi1", "cvp_clk"; clocks = <&clock_gcc GCC_VIDEO_AXI0_CLK>, <&clock_gcc GCC_VIDEO_AXI1_CLK>, <&clock_videocc VIDEO_CC_MVS1_CLK>; qcom,proxy-clock-names = "gcc_video_axi0", "gcc_video_axi1", "cvp_clk"; qcom,clock-configs = <0x0 0x0 0x1>; qcom,allowed-clock-rates = <403000000 520000000 549000000 666000000 800000000>; /* Buses */ bus_cnoc { compatible = "qcom,msm-cvp,bus"; label = "cnoc"; qcom,bus-master = <MSM_BUS_MASTER_AMPSS_M0>; qcom,bus-slave = <MSM_BUS_SLAVE_VENUS_CFG>; qcom,bus-governor = "performance"; qcom,bus-range-kbps = <1000 1000>; }; /* MMUs */ non_secure_cb { compatible = "qcom,msm-cvp,context-bank"; label = "cvp_hlos"; iommus = <&apps_smmu 0x2120 0x400>; qcom,iommu-dma = "disabled"; buffer-types = <0xfff>; virtual-addr-pool = <0x4b000000 0xe0000000>; }; /* Memory Heaps */ qcom,msm-cvp,mem_cdsp { compatible = "qcom,msm-cvp,mem-cdsp"; memory-region = <&cdsp_mem>; }; };
qcom/lahaina-cvp.dtsi 0 → 100644 +92 −0 Original line number Diff line number Diff line #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/soc/qcom,ipcc.h> #include <dt-bindings/interconnect/qcom,lahaina.h> #include <dt-bindings/clock/qcom,videocc-lahaina.h> &soc { msm_cvp: qcom,cvp@ab00000 { compatible = "qcom,msm-cvp", "qcom,lahaina-cvp"; status = "ok"; reg = <0xab00000 0x100000>; interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; /* LLCC Cache */ cache-slice-names = "cvp"; /* Supply */ cvp-supply = <&video_cc_mvs1c_gdsc>; cvp-core-supply = <&video_cc_mvs1_gdsc>; /* Clocks */ clock-names = "gcc_video_axi1", "cvp_clk", "core_clk"; clocks = <&clock_gcc GCC_VIDEO_AXI1_CLK>, <&clock_videocc VIDEO_CC_MVS1C_CLK>, <&clock_videocc VIDEO_CC_MVS1_CLK>; qcom,proxy-clock-names = "gcc_video_axi1", "cvp_clk", "core_clk"; qcom,clock-configs = <0x0 0x1 0x1>; qcom,allowed-clock-rates = <280000000 366000000 444000000>; resets = <&clock_videocc VIDEO_CC_MVS1C_CLK_ARES>; reset-names = "cvp_core_reset"; qcom,reg-presets = <0xB0088 0x0>; /* Buses */ cvp_cnoc { compatible = "qcom,msm-cvp,bus"; label = "cvp-cnoc"; qcom,bus-master = <MASTER_APPSS_PROC>; qcom,bus-slave = <SLAVE_VENUS_CFG>; qcom,bus-governor = "performance"; qcom,bus-range-kbps = <1000 1000>; }; cvp_bus_ddr { compatible = "qcom,msm-cvp,bus"; label = "cvp-ddr"; qcom,bus-master = <MASTER_VIDEO_PROC>; qcom,bus-slave = <SLAVE_EBI1>; qcom,bus-governor = "performance"; qcom,bus-range-kbps = <1000 6533000>; }; /* MMUs */ cvp_non_secure_cb { compatible = "qcom,msm-cvp,context-bank"; label = "cvp_hlos"; iommus = <&apps_smmu 0x2120 0x400>; buffer-types = <0xfff>; qcom,iommu-dma-addr-pool = <0x4b000000 0x90000000>; }; cvp_secure_nonpixel_cb { compatible = "qcom,msm-cvp,context-bank"; label = "cvp_sec_nonpixel"; iommus = <&apps_smmu 0x2124 0x400>; buffer-types = <0x741>; qcom,iommu-dma-addr-pool = <0x01000000 0x25800000>; qcom,iommu-vmid = <0xB>; }; cvp_secure_pixel_cb { compatible = "qcom,msm-cvp,context-bank"; label = "cvp_sec_pixel"; iommus = <&apps_smmu 0x2123 0x400>; buffer-types = <0x106>; qcom,iommu-dma-addr-pool = <0x26800000 0x24800000>; qcom,iommu-vmid = <0xA>; }; /* Memory Heaps */ qcom,msm-cvp,mem_cdsp { compatible = "qcom,msm-cvp,mem-cdsp"; memory-region = <&cdsp_mem>; }; }; };
qcom/lahaina.dtsi +19 −0 Original line number Diff line number Diff line Loading @@ -339,6 +339,15 @@ size = <0x0 0x800000>; }; cdsp_mem: cdsp_region { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; reusable; alignment = <0x0 0x400000>; size = <0x0 0x400000>; }; cdsp_secure_heap: cdsp_secure_heap@9b200000 { reg = <0x0 0x9b200000 0x0 0x4600000>; }; Loading Loading @@ -1683,6 +1692,15 @@ qcom,iommu-group = <>; }; }; qcom,cvpss@abb0000 { compatible = "qcom,pil-tz-generic"; reg = <0xabb0000 0x2000>; status = "ok"; qcom,pas-id = <26>; qcom,firmware-name = "cvpss"; memory-region = <&pil_cvp_mem>; }; }; #include "lahaina-regulators.dtsi" Loading @@ -1694,3 +1712,4 @@ #include "lahaina-pm.dtsi" #include "lahaina-qupv3.dtsi" #include "lahaina-vidc.dtsi" #include "lahaina-cvp.dtsi"
