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Commit 95ea5529 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2019-04-18' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Since Easter is looming for me, I'm just pushing whatever is in my
  tree, I'll see what else turns up and maybe I'll send another pull
  early next week if there is anything.

  tegra:
   - stream id programming fix
   - avoid divide by 0 for bad hdmi audio setup code

  ttm:
   - Hugepages fix
   - refcount imbalance in error path fix

  amdgpu:
   - GPU VM fixes for Vega/RV
   - DC AUX fix for active DP-DVI dongles
   - DC fix for multihead regression"

* tag 'drm-fixes-2019-04-18' of git://anongit.freedesktop.org/drm/drm:
  drm/tegra: hdmi: Setup audio only if configured
  drm/amd/display: If one stream full updates, full update all planes
  drm/amdgpu/gmc9: fix VM_L2_CNTL3 programming
  drm/amdgpu: shadow in shadow_list without tbo.mem.start cause page fault in sriov TDR
  gpu: host1x: Program stream ID to bypass without SMMU
  drm/amd/display: extending AUX SW Timeout
  drm/ttm: fix dma_fence refcount imbalance on error path
  drm/ttm: fix incrementing the page pointer for huge pages
  drm/ttm: fix start page for huge page check in ttm_put_pages()
  drm/ttm: fix out-of-bounds read in ttm_put_pages() v2
parents e53f31bf 00fd14ff

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+1 −0
Original line number Diff line number Diff line
@@ -3165,6 +3165,7 @@ static int amdgpu_device_recover_vram(struct amdgpu_device *adev) 


		/* No need to recover an evicted BO */

		if (shadow->tbo.mem.mem_type != TTM_PL_TT ||

		    shadow->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET ||

		    shadow->parent->tbo.mem.mem_type != TTM_PL_VRAM)

			continue;

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

+1 −0
Original line number Diff line number Diff line
@@ -182,6 +182,7 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev) 
		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,

				    L2_CACHE_BIGK_FRAGMENT_SIZE, 6);

	}

	WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp);



	tmp = mmVM_L2_CNTL4_DEFAULT;

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/display/dc/core/dc.c

+19 −0
Original line number Diff line number Diff line
@@ -1377,6 +1377,11 @@ static enum surface_update_type det_surface_update(const struct dc *dc, 
		return UPDATE_TYPE_FULL;

	}



	if (u->surface->force_full_update) {

		update_flags->bits.full_update = 1;

		return UPDATE_TYPE_FULL;

	}



	type = get_plane_info_update_type(u);

	elevate_update_type(&overall_type, type);
@@ -1802,6 +1807,14 @@ void dc_commit_updates_for_stream(struct dc *dc, 
		}



		dc_resource_state_copy_construct(state, context);



		for (i = 0; i < dc->res_pool->pipe_count; i++) {

			struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];

			struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];



			if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state)

				new_pipe->plane_state->force_full_update = true;

		}

	}
@@ -1838,6 +1851,12 @@ void dc_commit_updates_for_stream(struct dc *dc, 
		dc->current_state = context;

		dc_release_state(old);



		for (i = 0; i < dc->res_pool->pipe_count; i++) {

			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];



			if (pipe_ctx->plane_state && pipe_ctx->stream == stream)

				pipe_ctx->plane_state->force_full_update = false;

		}

	}

	/*let's use current_state to update watermark etc*/

	if (update_type >= UPDATE_TYPE_FULL)

drivers/gpu/drm/amd/display/dc/dc.h

+3 −0
Original line number Diff line number Diff line
@@ -503,6 +503,9 @@ struct dc_plane_state { 
	struct dc_plane_status status;

	struct dc_context *ctx;



	/* HACK: Workaround for forcing full reprogramming under some conditions */

	bool force_full_update;



	/* private to dc_surface.c */

	enum dc_irq_source irq_source;

	struct kref refcount;

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

+6 −3
Original line number Diff line number Diff line
@@ -190,6 +190,12 @@ static void submit_channel_request( 
				1,

				0);

	}



	REG_UPDATE(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, 1);



	REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 0,

				10, aux110->timeout_period/10);



	/* set the delay and the number of bytes to write */



	/* The length include
@@ -242,9 +248,6 @@ static void submit_channel_request( 
		}

	}



	REG_UPDATE(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, 1);

	REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 0,

				10, aux110->timeout_period/10);

	REG_UPDATE(AUX_SW_CONTROL, AUX_SW_GO, 1);

}