Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 95c1cd13 authored by Tomi Valkeinen's avatar Tomi Valkeinen
Browse files

arm/dts: dra7.dtsi: add DSS support 



DRA7xxx contains a very similar DSS to OMAP5. The main differences are:

* no DSI or RFBI support.
* 1 or 2 dedicated video PLLs.
* need to do additional configuration to the DRA7 CONTROL module.

DRA72xx has only one video PLL, and DRA74xx has two.

Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
Cc: devicetree@vger.kernel.org
Acked-by: default avatarTony Lindgren <tony@atomide.com>
parent 403ee909

arch/arm/boot/dts/dra7.dtsi

+38 −0
Original line number Diff line number Diff line
@@ -1474,6 +1474,44 @@ 
			clocks = <&sys_clkin1>;

			status = "disabled";

		};



		dss: dss@58000000 {

			compatible = "ti,dra7-dss";

			/* 'reg' defined in dra72x.dtsi and dra74x.dtsi */

			/* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */

			status = "disabled";

			ti,hwmods = "dss_core";

			/* CTRL_CORE_DSS_PLL_CONTROL */

			syscon-pll-ctrl = <&scm_conf 0x538>;

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;



			dispc@58001000 {

				compatible = "ti,dra7-dispc";

				reg = <0x58001000 0x1000>;

				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;

				ti,hwmods = "dss_dispc";

				clocks = <&dss_dss_clk>;

				clock-names = "fck";

				/* CTRL_CORE_SMA_SW_1 */

				syscon-pol = <&scm_conf 0x534>;

			};



			hdmi: encoder@58060000 {

				compatible = "ti,dra7-hdmi";

				reg = <0x58040000 0x200>,

				      <0x58040200 0x80>,

				      <0x58040300 0x80>,

				      <0x58060000 0x19000>;

				reg-names = "wp", "pll", "phy", "core";

				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;

				status = "disabled";

				ti,hwmods = "dss_hdmi";

				clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>;

				clock-names = "fck", "sys_clk";

			};

		};

	};



	thermal_zones: thermal-zones {

arch/arm/boot/dts/dra72x.dtsi

+11 −0
Original line number Diff line number Diff line
@@ -34,3 +34,14 @@ 
		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;

	};

};



&dss {

	reg = <0x58000000 0x80>,

	      <0x58004054 0x4>,

	      <0x58004300 0x20>;

	reg-names = "dss", "pll1_clkctrl", "pll1";



	clocks = <&dss_dss_clk>,

		 <&dss_video1_clk>;

	clock-names = "fck", "video1_clk";

};

arch/arm/boot/dts/dra74x.dtsi

+15 −0
Original line number Diff line number Diff line
@@ -73,3 +73,18 @@ 
		};

	};

};



&dss {

	reg = <0x58000000 0x80>,

	      <0x58004054 0x4>,

	      <0x58004300 0x20>,

	      <0x58005054 0x4>,

	      <0x58005300 0x20>;

	reg-names = "dss", "pll1_clkctrl", "pll1",

		    "pll2_clkctrl", "pll2";



	clocks = <&dss_dss_clk>,

		 <&dss_video1_clk>,

		 <&dss_video2_clk>;

	clock-names = "fck", "video1_clk", "video2_clk";

};