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Commit 9564f192 authored by Oak Zeng's avatar Oak Zeng Committed by Alex Deucher
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drm/amdgpu: Use asic specific doorbell index instead of macro definition 



ASIC specific doorbell layout is used instead of enum definition

Signed-off-by: default avatarOak Zeng <ozeng@amd.com>
Suggested-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Suggested-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6585661d

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

+8 −19
Original line number Diff line number Diff line
@@ -181,25 +181,14 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) 
			 * process in case of 64-bit doorbells so we

			 * can use each doorbell assignment twice.

			 */

			if (adev->asic_type == CHIP_VEGA10) {

			gpu_resources.sdma_doorbell[0][i] =

					AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 + (i >> 1);

				adev->doorbell_index.sdma_engine0 + (i >> 1);

			gpu_resources.sdma_doorbell[0][i+1] =

					AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 + 0x200 + (i >> 1);

				adev->doorbell_index.sdma_engine0 + 0x200 + (i >> 1);

			gpu_resources.sdma_doorbell[1][i] =

					AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 + (i >> 1);

				adev->doorbell_index.sdma_engine1 + (i >> 1);

			gpu_resources.sdma_doorbell[1][i+1] =

					AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 + 0x200 + (i >> 1);

			} else {

				gpu_resources.sdma_doorbell[0][i] =

					AMDGPU_DOORBELL64_sDMA_ENGINE0 + (i >> 1);

				gpu_resources.sdma_doorbell[0][i+1] =

					AMDGPU_DOORBELL64_sDMA_ENGINE0 + 0x200 + (i >> 1);

				gpu_resources.sdma_doorbell[1][i] =

					AMDGPU_DOORBELL64_sDMA_ENGINE1 + (i >> 1);

				gpu_resources.sdma_doorbell[1][i+1] =

					AMDGPU_DOORBELL64_sDMA_ENGINE1 + 0x200 + (i >> 1);

			}

				adev->doorbell_index.sdma_engine1 + 0x200 + (i >> 1);

		}

		/* Doorbells 0x0e0-0ff and 0x2e0-2ff are reserved for

		 * SDMA, IH and VCN. So don't use them for the CP.

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+1 −1
Original line number Diff line number Diff line
@@ -532,7 +532,7 @@ static int amdgpu_device_doorbell_init(struct amdgpu_device *adev) 
	adev->doorbell.size = pci_resource_len(adev->pdev, 2);



	adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),

					     AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);

					     adev->doorbell_index.max_assignment+1);

	if (adev->doorbell.num_doorbells == 0)

		return -EINVAL;

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

+1 −1
Original line number Diff line number Diff line
@@ -250,7 +250,7 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, 
	ring->adev = NULL;

	ring->ring_obj = NULL;

	ring->use_doorbell = true;

	ring->doorbell_index = AMDGPU_DOORBELL_KIQ;

	ring->doorbell_index = adev->doorbell_index.kiq;



	r = amdgpu_gfx_kiq_acquire(adev, ring);

	if (r)

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

+1 −1
Original line number Diff line number Diff line
@@ -4363,7 +4363,7 @@ static int gfx_v7_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 


	ring->ring_obj = NULL;

	ring->use_doorbell = true;

	ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + ring_id;

	ring->doorbell_index = adev->doorbell_index.mec_ring0 + ring_id;

	sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);



	irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+5 −5
Original line number Diff line number Diff line
@@ -1890,7 +1890,7 @@ static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 


	ring->ring_obj = NULL;

	ring->use_doorbell = true;

	ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + ring_id;

	ring->doorbell_index = adev->doorbell_index.mec_ring0 + ring_id;

	ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr

				+ (ring_id * GFX8_MEC_HPD_SIZE);

	sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
@@ -2001,7 +2001,7 @@ static int gfx_v8_0_sw_init(void *handle) 
		/* no gfx doorbells on iceland */

		if (adev->asic_type != CHIP_TOPAZ) {

			ring->use_doorbell = true;

			ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0;

			ring->doorbell_index = adev->doorbell_index.gfx_ring0;

		}



		r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq,
@@ -4215,7 +4215,7 @@ static void gfx_v8_0_set_cpg_door_bell(struct amdgpu_device *adev, struct amdgpu 


	tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,

					DOORBELL_RANGE_LOWER,

					AMDGPU_DOORBELL_GFX_RING0);

					adev->doorbell_index.gfx_ring0);

	WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);



	WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
@@ -4644,8 +4644,8 @@ static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring) 
static void gfx_v8_0_set_mec_doorbell_range(struct amdgpu_device *adev)

{

	if (adev->asic_type > CHIP_TONGA) {

		WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, AMDGPU_DOORBELL_KIQ << 2);

		WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, AMDGPU_DOORBELL_MEC_RING7 << 2);

		WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, adev->doorbell_index.kiq << 2);

		WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, adev->doorbell_index.mec_ring7 << 2);

	}

	/* enable doorbells */

	WREG32_FIELD(CP_PQ_STATUS, DOORBELL_ENABLE, 1);