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Commit 95626110 authored by Taniya Das's avatar Taniya Das Committed by Gerrit - the friendly Code Review server
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clk: qcom: clk-alpha-pll: Add support for Trion PLL 



Support Trion PLL ops which are required to be controlled from the HLOS
clock driver.

Change-Id: Ieb11cf72841c45ead2109b88c1ef0c85bdae2117
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 15c48e61

drivers/clk/qcom/clk-alpha-pll.c

+196 −1
Original line number Diff line number Diff line
@@ -198,7 +198,6 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); 


#define PLL_OPMODE_STANDBY	0x0

#define PLL_OPMODE_RUN		0x1



#define PLL_OUT_MASK	0x7

#define PLL_OUT_RATE_MARGIN	500
@@ -219,6 +218,9 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); 
/* FABIA PLL specific settings */

#define FABIA_PLL_CAL_VAL		0x3F



/* TRION PLL specific settings */

#define TRION_PCAL_DONE			BIT(26)



#define pll_alpha_width(p)					\

		((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ?	\

				 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
@@ -847,6 +849,85 @@ static int trion_pll_is_enabled(struct clk_alpha_pll *pll, 
				(mode_regval & PLL_OUTCTRL));

}



int clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

				const struct alpha_pll_config *config)

{

	int ret;



	if (!config) {

		pr_err("PLL configuration missing.\n");

		return -EINVAL;

	}



	if (trion_pll_is_enabled(pll, regmap)) {

		pr_warn("PLL is already enabled. Skipping configuration.\n");

		return 0;

	}



	if (config->l)

		regmap_write(regmap, PLL_L_VAL(pll), config->l);



	regmap_write(regmap, PLL_CAL_L_VAL(pll), LUCID_PLL_CAL_VAL);



	if (config->alpha)

		regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);



	if (config->config_ctl_val)

		regmap_write(regmap, PLL_CONFIG_CTL(pll),

						config->config_ctl_val);



	if (config->config_ctl_hi_val)

		regmap_write(regmap, PLL_CONFIG_CTL_U(pll),

						config->config_ctl_hi_val);



	if (config->config_ctl_hi1_val)

		regmap_write(regmap, PLL_CONFIG_CTL_U1(pll),

						config->config_ctl_hi1_val);



	if (config->user_ctl_val)

		regmap_write(regmap, PLL_USER_CTL(pll),

						config->user_ctl_val);



	if (config->user_ctl_hi_val)

		regmap_write(regmap, PLL_USER_CTL_U(pll),

						config->user_ctl_hi_val);



	if (config->user_ctl_hi1_val)

		regmap_write(regmap, PLL_USER_CTL_U1(pll),

						config->user_ctl_hi1_val);



	if (config->test_ctl_val)

		regmap_write(regmap, PLL_TEST_CTL(pll),

						config->test_ctl_val);



	if (config->test_ctl_hi_val)

		regmap_write(regmap, PLL_TEST_CTL_U(pll),

						config->test_ctl_hi_val);



	if (config->test_ctl_hi1_val)

		regmap_write(regmap, PLL_TEST_CTL_U1(pll),

						config->test_ctl_hi1_val);



	regmap_update_bits(regmap, + PLL_MODE(pll), PLL_UPDATE_BYPASS,

						PLL_UPDATE_BYPASS);



	/* Disable PLL output */

	ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);

	if (ret)

		return ret;



	/* Set operation mode to OFF */

	regmap_write(regmap, PLL_OPMODE(pll), PLL_OPMODE_STANDBY);



	/* PLL should be in OFF mode before continuing */

	wmb();



	/* Place the PLL in STANDBY mode */

	ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N,

							PLL_RESET_N);

	return ret;

}



static int clk_trion_pll_is_enabled(struct clk_hw *hw)

{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
@@ -936,6 +1017,103 @@ clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 
	return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);

}



static int clk_trion_pll_set_rate(struct clk_hw *hw, unsigned long rate,

				  unsigned long prate)

{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	unsigned long rrate;

	u32 regval, l, cal_val, alpha_width = pll_alpha_width(pll);

	u64 a;

	int ret;



	ret = regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);

	if (ret)

		return ret;



	ret = regmap_read(pll->clkr.regmap, PLL_CAL_L_VAL(pll), &cal_val);

	if (ret)

		return ret;



	/* PLL has lost it's L or CAL value, needs reconfiguration */

	if (!l || !cal_val) {

		ret = clk_trion_pll_configure(pll, pll->clkr.regmap,

						pll->config);

		if (ret) {

			pr_err("Failed to configure %s\n", clk_hw_get_name(hw));

			return ret;

		}

		pr_warn("%s: PLL configuration lost, reconfiguration of PLL done.\n",

				clk_hw_get_name(hw));

	}



	rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);

	/*

	 * Due to a limited number of bits for fractional rate programming, the

	 * rounded up rate could be marginally higher than the requested rate.

	 */

	if (rrate > (rate + PLL_OUT_RATE_MARGIN) || rrate < rate) {

		pr_err("Call set rate on the PLL with rounded rates!\n");

		return -EINVAL;

	}



	regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);

	regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);



	/* Latch the PLL input */

	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),

					PLL_UPDATE, PLL_UPDATE);

	if (ret)

		return ret;



	/* Wait for 2 reference cycles before checking the ACK bit. */

	udelay(1);

	regmap_read(pll->clkr.regmap, PLL_MODE(pll), &regval);

	if (!(regval & ALPHA_PLL_ACK_LATCH)) {

		WARN(1, "PLL latch failed. Output may be unstable!\n");

		return -EINVAL;

	}



	/* Return the latch input to 0 */

	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),

						PLL_UPDATE, 0);

	if (ret)

		return ret;



	if (clk_hw_is_enabled(hw)) {

		ret = wait_for_pll_enable_lock(pll);

		if (ret)

			return ret;

	}



	/* Wait for PLL output to stabilize */

	udelay(100);

	return 0;

}



static int clk_trion_pll_prepare(struct clk_hw *hw)

{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	u32 regval;

	int ret;



	ret = clk_prepare_regmap(hw);

	if (ret)

		return ret;



	/* Return early if calibration is not needed. */

	regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &regval);

	if (regval & TRION_PCAL_DONE)

		return ret;



	ret = clk_trion_pll_enable(hw);

	if (ret)

		return ret;



	clk_trion_pll_disable(hw);



	return 0;

}



static int __zonda_pll_is_enabled(struct clk_alpha_pll *pll,

					struct regmap *regmap)

{
@@ -1468,6 +1646,23 @@ const struct clk_ops clk_alpha_pll_hwfsm_ops = { 
};

EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);



const struct clk_ops clk_trion_pll_ops = {

	.prepare = clk_trion_pll_prepare,

	.unprepare = clk_unprepare_regmap,

	.pre_rate_change = clk_pre_change_regmap,

	.post_rate_change = clk_post_change_regmap,

	.enable = clk_trion_pll_enable,

	.disable = clk_trion_pll_disable,

	.is_enabled = clk_trion_pll_is_enabled,

	.recalc_rate = clk_trion_pll_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.set_rate = clk_trion_pll_set_rate,

#ifdef CONFIG_COMMON_CLK_QCOM_DEBUG

	.list_rate_vdd_level = clk_list_rate_vdd_level,

#endif

};

EXPORT_SYMBOL_GPL(clk_trion_pll_ops);



const struct clk_ops clk_trion_fixed_pll_ops = {

	.prepare = clk_prepare_regmap,

	.unprepare = clk_unprepare_regmap,

drivers/clk/qcom/clk-alpha-pll.h

+3 −0
Original line number Diff line number Diff line
@@ -151,6 +151,7 @@ extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops; 


extern const struct clk_ops clk_trion_fixed_pll_ops;

extern const struct clk_ops clk_trion_pll_postdiv_ops;

extern const struct clk_ops clk_trion_pll_ops;



void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

			     const struct alpha_pll_config *config);
@@ -166,4 +167,6 @@ int clk_lucid_5lpe_pll_configure(struct clk_alpha_pll *pll, 
int clk_zonda_5lpe_pll_configure(struct clk_alpha_pll *pll,

				struct regmap *regmap,

				const struct alpha_pll_config *config);

int clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

				const struct alpha_pll_config *config);

#endif