Merge tag 'mailbox-v4.19' of git://git.linaro.org/landing-teams/working/fujitsu/integration

NXP i.MX Messaging Unit (MU)

--------------------------------------------------------------------

The Messaging Unit module enables two processors within the SoC to

communicate and coordinate by passing messages (e.g. data, status

and control) through the MU interface. The MU also provides the ability

for one processor to signal the other processor using interrupts.

Because the MU manages the messaging between processors, the MU uses

different clocks (from each side of the different peripheral buses).

Therefore, the MU must synchronize the accesses from one side to the

other. The MU accomplishes synchronization using two sets of matching

registers (Processor A-facing, Processor B-facing).

Messaging Unit Device Node:

=============================

Required properties:

-------------------

- compatible :	should be "fsl,<chip>-mu", the supported chips include

		imx6sx, imx7s, imx8qxp, imx8qm.

		The "fsl,imx6sx-mu" compatible is seen as generic and should

		be included together with SoC specific compatible.

- reg :		Should contain the registers location and length

- interrupts :	Interrupt number. The interrupt specifier format depends

		on the interrupt controller parent.

- #mbox-cells:  Must be 2.

			  <&phandle type channel>

			    phandle   : Label name of controller

			    type      : Channel type

			    channel   : Channel number

		This MU support 4 type of unidirectional channels, each type

		has 4 channels. A total of 16 channels. Following types are

		supported:

		0 - TX channel with 32bit transmit register and IRQ transmit

		acknowledgment support.

		1 - RX channel with 32bit receive register and IRQ support

		2 - TX doorbell channel. Without own register and no ACK support.

		3 - RX doorbell channel.

Optional properties:

-------------------

- clocks :	phandle to the input clock.

- fsl,mu-side-b : Should be set for side B MU.

Examples:

--------

lsio_mu0: mailbox@5d1b0000 {

	compatible = "fsl,imx8qxp-mu";

	reg = <0x0 0x5d1b0000 0x0 0x10000>;

	interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;

	#mbox-cells = <2>;

};

MediaTek GCE

===============

The Global Command Engine (GCE) is used to help read/write registers with

critical time limitation, such as updating display configuration during the

vblank. The GCE can be used to implement the Command Queue (CMDQ) driver.

CMDQ driver uses mailbox framework for communication. Please refer to

mailbox.txt for generic information about mailbox device-tree bindings.

Required properties:

- compatible: Must be "mediatek,mt8173-gce"

- reg: Address range of the GCE unit

- interrupts: The interrupt signal from the GCE block

- clock: Clocks according to the common clock binding

- clock-names: Must be "gce" to stand for GCE clock

- #mbox-cells: Should be 3.

	<&phandle channel priority atomic_exec>

	phandle: Label name of a gce node.

	channel: Channel of mailbox. Be equal to the thread id of GCE.

	priority: Priority of GCE thread.

	atomic_exec: GCE processing continuous packets of commands in atomic

		way.

Required properties for a client device:

- mboxes: Client use mailbox to communicate with GCE, it should have this

  property and list of phandle, mailbox specifiers.

- mediatek,gce-subsys: u32, specify the sub-system id which is corresponding

  to the register address.

Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h'. Such as

sub-system ids, thread priority, event ids.

Example:

	gce: gce@10212000 {

		compatible = "mediatek,mt8173-gce";

		reg = <0 0x10212000 0 0x1000>;

		interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&infracfg CLK_INFRA_GCE>;

		clock-names = "gce";

		thread-num = CMDQ_THR_MAX_COUNT;

		#mbox-cells = <3>;

	};

Example for a client device:

	mmsys: clock-controller@14000000 {

		compatible = "mediatek,mt8173-mmsys";

		mboxes = <&gce 0 CMDQ_THR_PRIO_LOWEST 1>,

			 <&gce 1 CMDQ_THR_PRIO_LOWEST 1>;

		mediatek,gce-subsys = <SUBSYS_1400XXXX>;

		mutex-event-eof = <CMDQ_EVENT_MUTEX0_STREAM_EOF

				CMDQ_EVENT_MUTEX1_STREAM_EOF>;

		...

	};

Texas Instruments' Secure Proxy

========================================

The Texas Instruments' secure proxy is a mailbox controller that has

configurable queues selectable at SoC(System on Chip) integration. The

Message manager is broken up into different address regions that are

called "threads" or "proxies" - each instance is unidirectional and is

instantiated at SoC integration level by system controller to indicate

receive or transmit path.

Message Manager Device Node:

===========================

Required properties:

--------------------

- compatible:		Shall be "ti,am654-secure-proxy"

- reg-names 		target_data - Map the proxy data region

			rt - Map the realtime status region

			scfg - Map the configuration region

- reg:			Contains the register map per reg-names.

- #mbox-cells		Shall be 1 and shall refer to the transfer path

			called thread.

- interrupt-names:	Contains interrupt names matching the rx transfer path

			for a given SoC. Receive interrupts shall be of the

			format: "rx_<PID>".

- interrupts:		Contains the interrupt information corresponding to

			interrupt-names property.

Example(AM654):

------------

	secure_proxy: mailbox@32c00000 {

		compatible = "ti,am654-secure-proxy";

		#mbox-cells = <1>;

		reg-names = "target_data", "rt", "scfg";

		reg = <0x0 0x32c00000 0x0 0x100000>,

		      <0x0 0x32400000 0x0 0x100000>,

		      <0x0 0x32800000 0x0 0x100000>;

		interrupt-names = "rx_011";

		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

	};

	dmsc: dmsc {

		[...]

		mbox-names = "rx", "tx";

		# RX Thread ID is 11

		# TX Thread ID is 13

		mboxes= <&secure_proxy 11>,

			<&secure_proxy 13>;

		[...]

	};

	  The controller has 3 mailbox channels, the last of which can be

	  used in Secure mode only.

config IMX_MBOX

	tristate "i.MX Mailbox"

	depends on ARCH_MXC || COMPILE_TEST

	help

	  Mailbox implementation for i.MX Messaging Unit (MU).

config PLATFORM_MHU

	tristate "Platform MHU Mailbox"

	depends on OF

	  Mailbox implementation for STMicroelectonics STM32 family chips

	  with hardware for Inter-Processor Communication Controller (IPCC)

	  between processors. Say Y here if you want to have this support.

config MTK_CMDQ_MBOX

	tristate "MediaTek CMDQ Mailbox Support"

	depends on ARCH_MEDIATEK || COMPILE_TEST

	select MTK_INFRACFG

	help

	  Say yes here to add support for the MediaTek Command Queue (CMDQ)

	  mailbox driver. The CMDQ is used to help read/write registers with

	  critical time limitation, such as updating display configuration

	  during the vblank.

endif

obj-$(CONFIG_ARM_MHU)	+= arm_mhu.o

obj-$(CONFIG_IMX_MBOX)	+= imx-mailbox.o

obj-$(CONFIG_PLATFORM_MHU)	+= platform_mhu.o

obj-$(CONFIG_PL320_MBOX)	+= pl320-ipc.o

obj-$(CONFIG_TEGRA_HSP_MBOX)	+= tegra-hsp.o

obj-$(CONFIG_STM32_IPCC) 	+= stm32-ipcc.o

obj-$(CONFIG_MTK_CMDQ_MBOX)	+= mtk-cmdq-mailbox.o