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Commit 94ebc1fb authored by Jagadeesh Kona's avatar Jagadeesh Kona
Browse files

clk: qcom: Add clk_list_rates support for divider clocks 



Add clk_list_rates debugfs support for divider clocks to get all
the rates supported on divider clock.

Change-Id: Iebb18cfad4fded9a2704549a2b6429e06c2de36c
Signed-off-by: default avatarJagadeesh Kona <jkona@codeaurora.org>
parent ead4c53f

drivers/clk/qcom/clk-regmap-divider.c

+37 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2014, 2016-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2014, 2016-2020, The Linux Foundation. All rights reserved.

 */



#include <linux/kernel.h>
@@ -9,6 +9,7 @@ 
#include <linux/export.h>



#include "clk-regmap-divider.h"

#include "clk-debug.h"



static inline struct clk_regmap_div *to_clk_regmap_div(struct clk_hw *hw)

{
@@ -73,6 +74,39 @@ static unsigned long div_recalc_rate(struct clk_hw *hw, 
				   divider->width);

}



static long clk_regmap_div_list_rate(struct clk_hw *hw, unsigned int n,

		unsigned long fmax)

{

	struct clk_regmap_div *divider = to_clk_regmap_div(hw);

	struct clk_hw *parent_hw = clk_hw_get_parent(hw);

	struct clk_regmap *clkr = &divider->clkr;

	struct clk_regmap *parent_clkr = to_clk_regmap(parent_hw);

	u32 div;



	regmap_read(clkr->regmap, divider->reg, &div);

	div >>= divider->shift;

	div &= BIT(divider->width) - 1;

	div += 1;



	if (parent_clkr && parent_clkr->ops && parent_clkr->ops->list_rate)

		return (parent_clkr->ops->list_rate(parent_hw, n, fmax) / div);



	return -EINVAL;

}



static struct clk_regmap_ops clk_regmap_div_regmap_ops = {

	.list_rate = clk_regmap_div_list_rate,

};



static void clk_regmap_div_init(struct clk_hw *hw)

{

	struct clk_regmap_div *divider = to_clk_regmap_div(hw);

	struct clk_regmap *clkr = &divider->clkr;



	if (!clkr->ops)

		clkr->ops = &clk_regmap_div_regmap_ops;

}



const struct clk_ops clk_regmap_div_ops = {

	.round_rate = div_round_rate,

	.set_rate = div_set_rate,
@@ -83,5 +117,7 @@ EXPORT_SYMBOL_GPL(clk_regmap_div_ops); 
const struct clk_ops clk_regmap_div_ro_ops = {

	.round_rate = div_round_ro_rate,

	.recalc_rate = div_recalc_rate,

	.init = clk_regmap_div_init,

	.debug_init = clk_common_debug_init,

};

EXPORT_SYMBOL_GPL(clk_regmap_div_ro_ops);