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Commit 94e53262 authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Mauro Carvalho Chehab
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media: dt: bindings: Add binding for NVIDIA Tegra Video Decoder Engine 



Add binding documentation for the Video Decoder Engine which is found
on NVIDIA Tegra20/30/114/124/132 SoC's.

Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarHans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@s-opensource.com>
parent b32a2b42

Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt

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NVIDIA Tegra Video Decoder Engine



Required properties:

- compatible : Must contain one of the following values:

   - "nvidia,tegra20-vde"

   - "nvidia,tegra30-vde"

   - "nvidia,tegra114-vde"

   - "nvidia,tegra124-vde"

   - "nvidia,tegra132-vde"

- reg : Must contain an entry for each entry in reg-names.

- reg-names : Must include the following entries:

  - sxe

  - bsev

  - mbe

  - ppe

  - mce

  - tfe

  - ppb

  - vdma

  - frameid

- iram : Must contain phandle to the mmio-sram device node that represents

         IRAM region used by VDE.

- interrupts : Must contain an entry for each entry in interrupt-names.

- interrupt-names : Must include the following entries:

  - sync-token

  - bsev

  - sxe

- clocks : Must include the following entries:

  - vde

- resets : Must include the following entries:

  - vde



Example:



video-codec@6001a000 {

	compatible = "nvidia,tegra20-vde";

	reg = <0x6001a000 0x1000 /* Syntax Engine */

	       0x6001b000 0x1000 /* Video Bitstream Engine */

	       0x6001c000  0x100 /* Macroblock Engine */

	       0x6001c200  0x100 /* Post-processing Engine */

	       0x6001c400  0x100 /* Motion Compensation Engine */

	       0x6001c600  0x100 /* Transform Engine */

	       0x6001c800  0x100 /* Pixel prediction block */

	       0x6001ca00  0x100 /* Video DMA */

	       0x6001d800  0x300 /* Video frame controls */>;

	reg-names = "sxe", "bsev", "mbe", "ppe", "mce",

		    "tfe", "ppb", "vdma", "frameid";

	iram = <&vde_pool>; /* IRAM region */

	interrupts = <GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */

		     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */

		     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */

	interrupt-names = "sync-token", "bsev", "sxe";

	clocks = <&tegra_car TEGRA20_CLK_VDE>;

	resets = <&tegra_car 61>;

};