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Commit 94acdb19 authored by Raghavendra Kakarla's avatar Raghavendra Kakarla
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ARM: dts: msm: Add the interrupts for the APPS TGU for holi 

Update the APSS TGU node with interrupt numbers and corrected
the number of registers supported.

Change-Id: Idacedd7eea864bc2dfc0d58ec7333d1038a1a1a0
parent 540e981f

bindings/arm/coresight.txt

+7 −2
Original line number Diff line number Diff line
@@ -137,9 +137,10 @@ its hardware characteristcs. 
	* arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely

	  use the SG mode on this system.



* Optional property for CATU :

* Optional property for CATU and APSS :

	* interrupts : Exactly one SPI may be listed for reporting the address

	  error

	  error for CATU and four interrupts for TGU to get trigger from four

	  type of events.



* Required property for TPDAs:
@@ -480,6 +481,10 @@ Example: 
		tgu-conditions = <4>;

		tgu-regs = <4>;

		tgu-timer-counters = <8>;

		interrupts = <GIC_SPI 23 IRQ_TYPE_TRIGGER_HIGH>,

			     <GIC_SPI 24 IRQ_TYPE_TRIGGER_HIGH>,

			     <GIC_SPI 25 IRQ_TYPE_TRIGGER_HIGH>,

			     <GIC_SPI 26 IRQ_TYPE_TRIGGER_HIGH>;



		coresight-name = "coresight-tgu-ipcb";

qcom/holi-coresight.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -45,9 +45,9 @@ 
		reg-names = "tgu-base";

		tgu-steps = <3>;

		tgu-conditions = <4>;

		tgu-regs = <4>;

		tgu-regs = <8>;

		tgu-timer-counters = <8>;



		interrupts = <0 23 1>, <0 24 1>, <0 25 1>, <0 26 1>;

		coresight-name = "coresight-tgu-apss";



		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;