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Commit 9498dba7 authored by Mika Kuoppala's avatar Mika Kuoppala Committed by Mika Kuoppala
Browse files

drm/i915/kbl: Add WaDisableSDEUnitClockGating 



Add this workaround until upto kbl revid B0.

References: HSD#1802092
Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: default avatarMatthew Auld <matthew.auld@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465309159-30531-10-git-send-email-mika.kuoppala@intel.com
parent 8401d42f

drivers/gpu/drm/i915/intel_pm.c

+16 −2
Original line number Diff line number Diff line
@@ -6963,11 +6963,25 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv, 
	I915_WRITE(GEN7_MISCCPCTL, misccpctl);

}



static void kabylake_init_clock_gating(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	/* See Bspec note for PSR2_CTL bit 31, Wa#828:kbl */

	I915_WRITE(CHICKEN_PAR1_1,

		   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);



	/* WaDisableSDEUnitClockGating:kbl */

	if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))

		I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |

			   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);

}



static void skylake_init_clock_gating(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,kbl */

	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl */

	I915_WRITE(CHICKEN_PAR1_1,

		   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);

}
@@ -7433,7 +7447,7 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) 
	if (IS_SKYLAKE(dev_priv))

		dev_priv->display.init_clock_gating = skylake_init_clock_gating;

	else if (IS_KABYLAKE(dev_priv))

		dev_priv->display.init_clock_gating = skylake_init_clock_gating;

		dev_priv->display.init_clock_gating = kabylake_init_clock_gating;

	else if (IS_BROXTON(dev_priv))

		dev_priv->display.init_clock_gating = bxt_init_clock_gating;

	else if (IS_BROADWELL(dev_priv))