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Unverified Commit 94613d5a authored by Patrice Chotard's avatar Patrice Chotard Committed by Mark Brown
Browse files

spi: spi-stm32-qspi: Remove CR_FTHRES_MASK usage 



On STM32 F4/F7/H7 SoCs, FTHRES is a 5 bits field in QSPI_CR register,
but for STM32MP1 SoCs, FTHRES is a 4 bits field long. CR_FTHRES_MASK
definition is not correct.

As for all these SoCs, FTHRES field is set to 3, FIELD_PREP() macro
is used with a constant as second parameter which make its usage useless.

CR_FTHRES_MASK and FIELD_PREP() can be removed.

Signed-off-by: default avatarPatrice Chotard <patrice.chotard@st.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent a75e91ba

drivers/spi/spi-stm32-qspi.c

+2 −2
Original line number Diff line number Diff line
@@ -29,7 +29,7 @@ 
#define CR_SSHIFT		BIT(4)

#define CR_DFM			BIT(6)

#define CR_FSEL			BIT(7)

#define CR_FTHRES_MASK		GENMASK(12, 8)

#define CR_FTHRES_SHIFT		8

#define CR_TEIE			BIT(16)

#define CR_TCIE			BIT(17)

#define CR_FTIE			BIT(18)
@@ -463,7 +463,7 @@ static int stm32_qspi_setup(struct spi_device *spi) 
	flash->presc = presc;



	mutex_lock(&qspi->lock);

	qspi->cr_reg = FIELD_PREP(CR_FTHRES_MASK, 3) | CR_SSHIFT | CR_EN;

	qspi->cr_reg = 3 << CR_FTHRES_SHIFT | CR_SSHIFT | CR_EN;

	writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);



	/* set dcr fsize to max address */