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Commit 942d1cf4 authored by Vandita Kulkarni's avatar Vandita Kulkarni Committed by Jani Nikula
Browse files

drm/i915/icl: Fix port disable sequence for mipi-dsi 



Re-enable clock gating of DDI clocks.

v2: Fix the default ddi clk state for mipi-dsi (Imre)

Fixes: 1026bea0 ("drm/i915/icl: Ungate DSI clocks")
Signed-off-by: default avatarVandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: default avatarUma Shankar <uma.shankar@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1553513202-13863-2-git-send-email-vandita.kulkarni@intel.com
parent c5b81a32

drivers/gpu/drm/i915/icl_dsi.c

+1 −1
Original line number Diff line number Diff line
@@ -1138,7 +1138,7 @@ static void gen11_dsi_disable_port(struct intel_encoder *encoder) 
			DRM_ERROR("DDI port:%c buffer not idle\n",

				  port_name(port));

	}

	gen11_dsi_ungate_clocks(encoder);

	gen11_dsi_gate_clocks(encoder);

}



static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)

drivers/gpu/drm/i915/intel_ddi.c

+3 −3
Original line number Diff line number Diff line
@@ -2802,10 +2802,10 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 
				return;

		}

		/*

		 * DSI ports should have their DDI clock ungated when disabled

		 * and gated when enabled.

		 * For DSI we keep the ddi clocks gated

		 * except during enable/disable sequence.

		 */

		ddi_clk_needed = !encoder->base.crtc;

		ddi_clk_needed = false;

	}



	val = I915_READ(DPCLKA_CFGCR0_ICL);