Loading qcom/lahaina-pinctrl.dtsi +13 −0 Original line number Diff line number Diff line Loading @@ -2926,6 +2926,19 @@ }; }; }; usb3phy_portselect_default: usb3phy_portselect_default { mux { pins = "gpio81"; function = "usb_phy"; }; config { pins = "gpio81"; bias-disable; drive-strength = <2>; }; }; }; pmx_sde: pmx_sde { Loading qcom/lahaina-usb.dtsi +4 −0 Original line number Diff line number Diff line Loading @@ -145,6 +145,10 @@ resets = <&clock_gcc GCC_USB3_DP_PHY_PRIM_BCR>, <&clock_gcc GCC_USB3_PHY_PRIM_BCR>; reset-names = "global_phy_reset", "phy_reset"; pinctrl-names = "default"; pinctrl-0 = <&usb3phy_portselect_default>; qcom,qmp-phy-reg-offset = <USB3_DP_PCS_PCS_STATUS1 USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL Loading Loading
qcom/lahaina-pinctrl.dtsi +13 −0 Original line number Diff line number Diff line Loading @@ -2926,6 +2926,19 @@ }; }; }; usb3phy_portselect_default: usb3phy_portselect_default { mux { pins = "gpio81"; function = "usb_phy"; }; config { pins = "gpio81"; bias-disable; drive-strength = <2>; }; }; }; pmx_sde: pmx_sde { Loading
qcom/lahaina-usb.dtsi +4 −0 Original line number Diff line number Diff line Loading @@ -145,6 +145,10 @@ resets = <&clock_gcc GCC_USB3_DP_PHY_PRIM_BCR>, <&clock_gcc GCC_USB3_PHY_PRIM_BCR>; reset-names = "global_phy_reset", "phy_reset"; pinctrl-names = "default"; pinctrl-0 = <&usb3phy_portselect_default>; qcom,qmp-phy-reg-offset = <USB3_DP_PCS_PCS_STATUS1 USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL Loading