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Commit 9405447e authored by Marc Zyngier's avatar Marc Zyngier Committed by Will Deacon
Browse files

arm64: Avoid Cavium TX2 erratum 219 when switching TTBR 



As a PRFM instruction racing against a TTBR update can have undesirable
effects on TX2, NOP-out such PRFM on cores that are affected by
the TX2-219 erratum.

Cc: <stable@vger.kernel.org>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 93916beb

arch/arm64/include/asm/cpucaps.h

+2 −1
Original line number Diff line number Diff line
@@ -53,7 +53,8 @@ 
#define ARM64_HAS_DCPODP			43

#define ARM64_WORKAROUND_1463225		44

#define ARM64_WORKAROUND_CAVIUM_TX2_219_TVM	45

#define ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM	46



#define ARM64_NCAPS				46

#define ARM64_NCAPS				47



#endif /* __ASM_CPUCAPS_H */

arch/arm64/kernel/cpu_errata.c

+5 −0
Original line number Diff line number Diff line
@@ -884,6 +884,11 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),

		.matches = needs_tx2_tvm_workaround,

	},

	{

		.desc = "Cavium ThunderX2 erratum 219 (PRFM removal)",

		.capability = ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM,

		ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),

	},

#endif

	{

	}

arch/arm64/kernel/entry.S

+2 −0
Original line number Diff line number Diff line
@@ -1070,7 +1070,9 @@ alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003 
#else

	ldr	x30, =vectors

#endif

alternative_if_not ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM

	prfm	plil1strm, [x30, #(1b - tramp_vectors)]

alternative_else_nop_endif

	msr	vbar_el1, x30

	add	x30, x30, #(1b - tramp_vectors)

	isb