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Commit 93e2ca02 authored by Dong Aisheng's avatar Dong Aisheng Committed by Shawn Guo
Browse files

ARM: dts: imx6qdl: add uhs pinctrl state for usdhc3 



This is needed for supporting ultra high speed cards like SD3.0 cards.

Signed-off-by: default avatarDong Aisheng <b29396@freescale.com>
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
parent 640a7f3f

arch/arm/boot/dts/imx6qdl-sabreauto.dtsi

+4 −1
Original line number Diff line number Diff line
@@ -54,6 +54,7 @@ 
			fsl,pins = <

				MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000

				MX6QDL_PAD_SD2_DAT2__GPIO1_IO13  0x80000000

				MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059

			>;

		};

	};
@@ -74,8 +75,10 @@ 
};



&usdhc3 {

	pinctrl-names = "default";

	pinctrl-names = "default", "state_100mhz", "state_200mhz";

	pinctrl-0 = <&pinctrl_usdhc3_1>;

	pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>;

	pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>;

	cd-gpios = <&gpio6 15 0>;

	wp-gpios = <&gpio1 13 0>;

	status = "okay";

arch/arm/boot/dts/imx6qdl.dtsi

+30 −0
Original line number Diff line number Diff line
@@ -1205,6 +1205,36 @@ 
						>;

					};



					pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { /* 100Mhz */

						fsl,pins = <

							MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9

							MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9

							MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9

							MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9

							MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9

							MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9

							MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9

							MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9

							MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9

							MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9

						>;

					};



					pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { /* 200Mhz */

						fsl,pins = <

							MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9

							MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9

							MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9

							MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9

							MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9

							MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9

							MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9

							MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9

							MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9

							MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9

						>;

					};



					pinctrl_usdhc3_2: usdhc3grp-2 {

						fsl,pins = <

							MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059