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Commit 936fd005 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 fixes from Thomas Gleixner:
 "A couple of fixes addressing the following issues:

   - The last polishing for the TLB code, removing the last BUG_ON() and
     the debug file along with tidying up the lazy TLB code.

   - Prevent triple fault on 1st Gen. 486 caused by stupidly calling the
     early IDT setup after the first function which causes a fault which
     should be caught by the exception table.

   - Limit the mmap of /dev/mem to valid addresses

   - Prevent late microcode loading on Broadwell X

   - Remove a redundant assignment in the cache info code"

* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/mm: Limit mmap() of /dev/mem to valid physical addresses
  x86/mm: Remove debug/x86/tlb_defer_switch_to_init_mm
  x86/mm: Tidy up "x86/mm: Flush more aggressively in lazy TLB mode"
  x86/mm/64: Remove the last VM_BUG_ON() from the TLB code
  x86/microcode/intel: Disable late loading on model 79
  x86/idt: Initialize early IDT before cr4_init_shadow()
  x86/cpu/intel_cacheinfo: Remove redundant assignment to 'this_leaf'
parents 9e415a8e ce56a86e

arch/x86/include/asm/io.h

+4 −0
Original line number Original line Diff line number Diff line
@@ -110,6 +110,10 @@ build_mmio_write(__writeq, "q", unsigned long, "r", ) 




#endif

#endif





#define ARCH_HAS_VALID_PHYS_ADDR_RANGE

extern int valid_phys_addr_range(phys_addr_t addr, size_t size);

extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);



/**

/**

 *	virt_to_phys	-	map virtual addresses to physical

 *	virt_to_phys	-	map virtual addresses to physical

 *	@address: address to remap

 *	@address: address to remap

arch/x86/include/asm/tlbflush.h

+15 −6
Original line number Original line Diff line number Diff line
@@ -82,12 +82,21 @@ static inline u64 inc_mm_tlb_gen(struct mm_struct *mm) 
#define __flush_tlb_single(addr) __native_flush_tlb_single(addr)

#define __flush_tlb_single(addr) __native_flush_tlb_single(addr)

#endif

#endif





static inline bool tlb_defer_switch_to_init_mm(void)

{

	/*

	/*

 * If tlb_use_lazy_mode is true, then we try to avoid switching CR3 to point

	 * If we have PCID, then switching to init_mm is reasonably

 * to init_mm when we switch to a kernel thread (e.g. the idle thread).  If

	 * fast.  If we don't have PCID, then switching to init_mm is

 * it's false, then we immediately switch CR3 when entering a kernel thread.

	 * quite slow, so we try to defer it in the hopes that we can

	 * avoid it entirely.  The latter approach runs the risk of

	 * receiving otherwise unnecessary IPIs.

	 *

	 * This choice is just a heuristic.  The tlb code can handle this

	 * function returning true or false regardless of whether we have

	 * PCID.

	 */

	 */

DECLARE_STATIC_KEY_TRUE(tlb_use_lazy_mode);

	return !static_cpu_has(X86_FEATURE_PCID);

}





/*

/*

 * 6 because 6 should be plenty and struct tlb_state will fit in

 * 6 because 6 should be plenty and struct tlb_state will fit in

arch/x86/kernel/cpu/intel_cacheinfo.c

+0 −1
Original line number Original line Diff line number Diff line
@@ -831,7 +831,6 @@ static int __cache_amd_cpumap_setup(unsigned int cpu, int index, 
	} else if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {

	} else if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {

		unsigned int apicid, nshared, first, last;

		unsigned int apicid, nshared, first, last;





		this_leaf = this_cpu_ci->info_list + index;

		nshared = base->eax.split.num_threads_sharing + 1;

		nshared = base->eax.split.num_threads_sharing + 1;

		apicid = cpu_data(cpu).apicid;

		apicid = cpu_data(cpu).apicid;

		first = apicid - (apicid % nshared);

		first = apicid - (apicid % nshared);

arch/x86/kernel/cpu/microcode/intel.c

+19 −0
Original line number Original line Diff line number Diff line
@@ -34,6 +34,7 @@ 
#include <linux/mm.h>

#include <linux/mm.h>





#include <asm/microcode_intel.h>

#include <asm/microcode_intel.h>

#include <asm/intel-family.h>

#include <asm/processor.h>

#include <asm/processor.h>

#include <asm/tlbflush.h>

#include <asm/tlbflush.h>

#include <asm/setup.h>

#include <asm/setup.h>
@@ -918,6 +919,18 @@ static int get_ucode_fw(void *to, const void *from, size_t n) 
	return 0;

	return 0;

}

}





static bool is_blacklisted(unsigned int cpu)

{

	struct cpuinfo_x86 *c = &cpu_data(cpu);



	if (c->x86 == 6 && c->x86_model == INTEL_FAM6_BROADWELL_X) {

		pr_err_once("late loading on model 79 is disabled.\n");

		return true;

	}



	return false;

}



static enum ucode_state request_microcode_fw(int cpu, struct device *device,

static enum ucode_state request_microcode_fw(int cpu, struct device *device,

					     bool refresh_fw)

					     bool refresh_fw)

{

{
@@ -926,6 +939,9 @@ static enum ucode_state request_microcode_fw(int cpu, struct device *device, 
	const struct firmware *firmware;

	const struct firmware *firmware;

	enum ucode_state ret;

	enum ucode_state ret;





	if (is_blacklisted(cpu))

		return UCODE_NFOUND;



	sprintf(name, "intel-ucode/%02x-%02x-%02x",

	sprintf(name, "intel-ucode/%02x-%02x-%02x",

		c->x86, c->x86_model, c->x86_mask);

		c->x86, c->x86_model, c->x86_mask);
@@ -950,6 +966,9 @@ static int get_ucode_user(void *to, const void *from, size_t n) 
static enum ucode_state

static enum ucode_state

request_microcode_user(int cpu, const void __user *buf, size_t size)

request_microcode_user(int cpu, const void __user *buf, size_t size)

{

{

	if (is_blacklisted(cpu))

		return UCODE_NFOUND;



	return generic_load_microcode(cpu, (void *)buf, size, &get_ucode_user);

	return generic_load_microcode(cpu, (void *)buf, size, &get_ucode_user);

}

}

arch/x86/kernel/head32.c

+3 −2
Original line number Original line Diff line number Diff line
@@ -30,10 +30,11 @@ static void __init i386_default_early_setup(void) 




asmlinkage __visible void __init i386_start_kernel(void)

asmlinkage __visible void __init i386_start_kernel(void)

{

{

	cr4_init_shadow();

	/* Make sure IDT is set up before any exception happens */



	idt_setup_early_handler();

	idt_setup_early_handler();





	cr4_init_shadow();



	sanitize_boot_params(&boot_params);

	sanitize_boot_params(&boot_params);





	x86_early_init_platform_quirks();

	x86_early_init_platform_quirks();