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Commit 936896e9 authored by Achiad Shochat's avatar Achiad Shochat Committed by David S. Miller
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net/mlx5e: Make RSS indirection table size a constant 



The indirection table size was defined by a variable that
was actually assigned a constant value.
Since we do not have any forseen intension to make it configurable
we simply made it a constant.

We also limit the number of channels such that the RSS indirection
table could always populate all RX rings.

Signed-off-by: default avatarAchiad Shochat <achiad@mellanox.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 57afead5

drivers/net/ethernet/mellanox/mlx5/core/en.h

+3 −2
Original line number Diff line number Diff line
@@ -56,8 +56,10 @@ 
#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC      0x10

#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS      0x20

#define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES                0x80

#define MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ         0x7



#define MLX5E_LOG_INDIR_RQT_SIZE       0x7

#define MLX5E_INDIR_RQT_SIZE           BIT(MLX5E_LOG_INDIR_RQT_SIZE)

#define MLX5E_MAX_NUM_CHANNELS         (MLX5E_INDIR_RQT_SIZE >> 1)

#define MLX5E_TX_CQ_POLL_BUDGET        128

#define MLX5E_UPDATE_STATS_INTERVAL    200 /* msecs */

#define MLX5E_SQ_BF_BUDGET             16
@@ -268,7 +270,6 @@ struct mlx5e_params { 
	u16 tx_cq_moderation_usec;

	u16 tx_cq_moderation_pkts;

	u16 min_rx_wqes;

	u16 rx_hash_log_tbl_sz;

	bool lro_en;

	u32 lro_wqe_sz;

	u8  rss_hfunc;

drivers/net/ethernet/mellanox/mlx5/core/en_main.c

+27 −33
Original line number Diff line number Diff line
@@ -1174,20 +1174,15 @@ static int mlx5e_bits_invert(unsigned long a, int size) 
	return inv;

}



static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, void *rqtc,

				enum mlx5e_rqt_ix rqt_ix)

static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)

{

	int i;

	int log_sz;



	switch (rqt_ix) {

	case MLX5E_INDIRECTION_RQT:

		log_sz = priv->params.rx_hash_log_tbl_sz;

		for (i = 0; i < (1 << log_sz); i++) {

	for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {

		int ix = i;



		if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)

				ix = mlx5e_bits_invert(i, log_sz);

			ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);



		ix = ix % priv->params.num_channels;

		MLX5_SET(rqtc, rqtc, rq_num[i],
@@ -1195,6 +1190,15 @@ static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, void *rqtc, 
			 priv->channel[ix]->rq.rqn :

			 priv->drop_rq.rqn);

	}

}



static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, void *rqtc,

				enum mlx5e_rqt_ix rqt_ix)

{



	switch (rqt_ix) {

	case MLX5E_INDIRECTION_RQT:

		mlx5e_fill_indir_rqt_rqns(priv, rqtc);



		break;
@@ -1214,13 +1218,10 @@ static int mlx5e_create_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix) 
	u32 *in;

	void *rqtc;

	int inlen;

	int log_sz;

	int sz;

	int err;



	log_sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 0 :

		  priv->params.rx_hash_log_tbl_sz;

	sz = 1 << log_sz;

	sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;



	inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;

	in = mlx5_vzalloc(inlen);
@@ -1247,13 +1248,10 @@ static int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix) 
	u32 *in;

	void *rqtc;

	int inlen;

	int log_sz;

	int sz;

	int err;



	log_sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 0 :

		  priv->params.rx_hash_log_tbl_sz;

	sz = 1 << log_sz;

	sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;



	inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;

	in = mlx5_vzalloc(inlen);
@@ -1911,7 +1909,7 @@ u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev) 


static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,

				    struct net_device *netdev,

				    int num_comp_vectors)

				    int num_channels)

{

	struct mlx5e_priv *priv = netdev_priv(netdev);
@@ -1930,11 +1928,6 @@ static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev, 
	priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);

	priv->params.min_rx_wqes           =

		MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;

	priv->params.rx_hash_log_tbl_sz    =

		(order_base_2(num_comp_vectors) >

		 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?

		order_base_2(num_comp_vectors)           :

		MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;

	priv->params.num_tc                = 1;

	priv->params.default_vlan_prio     = 0;

	priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
@@ -1948,7 +1941,7 @@ static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev, 


	priv->mdev                         = mdev;

	priv->netdev                       = netdev;

	priv->params.num_channels          = num_comp_vectors;

	priv->params.num_channels          = num_channels;

	priv->default_vlan_prio            = priv->params.default_vlan_prio;



	spin_lock_init(&priv->async_events_spinlock);
@@ -2037,19 +2030,20 @@ static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev) 
{

	struct net_device *netdev;

	struct mlx5e_priv *priv;

	int ncv = mdev->priv.eq_table.num_comp_vectors;

	int nch = min_t(int, mdev->priv.eq_table.num_comp_vectors,

			MLX5E_MAX_NUM_CHANNELS);

	int err;



	if (mlx5e_check_required_hca_cap(mdev))

		return NULL;



	netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), ncv, ncv);

	netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), nch, nch);

	if (!netdev) {

		mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");

		return NULL;

	}



	mlx5e_build_netdev_priv(mdev, netdev, ncv);

	mlx5e_build_netdev_priv(mdev, netdev, nch);

	mlx5e_build_netdev(netdev);



	netif_carrier_off(netdev);