Loading asoc/msm-dai-q6-v2.c +13 −0 Original line number Diff line number Diff line Loading @@ -284,6 +284,7 @@ struct msm_dai_q6_cdc_dma_dai_data { u32 is_island_dai; u32 xt_logging_disable; union afe_port_config port_config; u32 cdc_dma_data_align; }; struct msm_dai_q6_auxpcm_dai_data { Loading Loading @@ -12341,6 +12342,12 @@ static int msm_dai_q6_cdc_dma_prepare(struct snd_pcm_substream *substream, dai_data->port_config.cdc_dma.data_format = AFE_LINEAR_PCM_DATA_PACKED_16BIT; rc = afe_send_cdc_dma_data_align(dai->id, dai_data->cdc_dma_data_align); if (rc) pr_debug("%s: afe send data alignment failed %d\n", __func__, rc); rc = afe_port_start(dai->id, &dai_data->port_config, dai_data->rate); if (rc < 0) Loading Loading @@ -12987,6 +12994,12 @@ static int msm_dai_q6_cdc_dma_dev_probe(struct platform_device *pdev) if (rc) dev_dbg(&pdev->dev, "island supported entry not found\n"); rc = of_property_read_u32(pdev->dev.of_node, "qcom,msm-cdc-dma-data-align", &dai_data->cdc_dma_data_align); if (rc) dev_dbg(&pdev->dev, "cdc dma data align supported entry not found\n"); dev_set_drvdata(&pdev->dev, dai_data); for (i = 0; i < ARRAY_SIZE(msm_dai_q6_cdc_dma_dai); i++) { Loading dsp/q6afe.c +43 −0 Original line number Diff line number Diff line Loading @@ -2593,6 +2593,49 @@ static void afe_send_cal_spkr_prot_rx(int port_id) return; } /** * afe_send_cdc_dma_data_align - * for sending codec dma data alignment * * @port_id: AFE port id number */ int afe_send_cdc_dma_data_align(u16 port_id, u32 cdc_dma_data_align) { struct afe_param_id_cdc_dma_data_align data_align; struct param_hdr_v3 param_info; uint16_t port_index = 0; int ret = -EINVAL; memset(&data_align, 0, sizeof(data_align)); memset(¶m_info, 0, sizeof(param_info)); port_index = afe_get_port_index(port_id); if (port_index < 0 || port_index >= AFE_MAX_PORTS) { pr_err("%s: AFE port index[%d] invalid!\n", __func__, port_index); return -EINVAL; } data_align.cdc_dma_data_align = cdc_dma_data_align; pr_debug("%s: port_id %x, data_align %d\n", __func__, port_id, data_align.cdc_dma_data_align); param_info.module_id = AFE_MODULE_AUDIO_DEV_INTERFACE; param_info.instance_id = INSTANCE_ID_0; param_info.param_id = AFE_PARAM_ID_CODEC_DMA_DATA_ALIGN; param_info.param_size = sizeof(data_align); ret = q6afe_pack_and_set_param_in_band(port_id, q6audio_get_port_index(port_id), param_info, (u8 *) &data_align); if (ret) pr_err("%s: AFE cdc cdc data alignment for port 0x%x failed %d\n", __func__, port_id, ret); return ret; } EXPORT_SYMBOL(afe_send_cdc_dma_data_align); static int afe_send_hw_delay(u16 port_id, u32 rate) { struct audio_cal_hw_delay_entry delay_entry; Loading include/dsp/apr_audio-v2.h +6 −0 Original line number Diff line number Diff line Loading @@ -3951,6 +3951,12 @@ struct afe_param_id_set_topology_cfg { u32 topology_id; } __packed; #define AFE_PARAM_ID_CODEC_DMA_DATA_ALIGN 0x000102EA struct afe_param_id_cdc_dma_data_align { uint32_t cdc_dma_data_align; } __packed; #define MAX_ABR_LEVELS 5 struct afe_bit_rate_level_map_t { Loading include/dsp/q6afe-v2.h +1 −0 Original line number Diff line number Diff line Loading @@ -395,6 +395,7 @@ void afe_set_vad_cfg(u32 vad_enable, u32 preroll_config, u32 port_id); void afe_set_island_mode_cfg(u16 port_id, u32 enable_flag); void afe_get_island_mode_cfg(u16 port_id, u32 *enable_flag); int afe_send_cdc_dma_data_align(u16 port_id, u32 cdc_dma_data_align); int afe_port_start(u16 port_id, union afe_port_config *afe_config, u32 rate); int afe_set_tws_channel_mode(u32 foramt, u16 port_id, u32 channel_mode); Loading Loading
asoc/msm-dai-q6-v2.c +13 −0 Original line number Diff line number Diff line Loading @@ -284,6 +284,7 @@ struct msm_dai_q6_cdc_dma_dai_data { u32 is_island_dai; u32 xt_logging_disable; union afe_port_config port_config; u32 cdc_dma_data_align; }; struct msm_dai_q6_auxpcm_dai_data { Loading Loading @@ -12341,6 +12342,12 @@ static int msm_dai_q6_cdc_dma_prepare(struct snd_pcm_substream *substream, dai_data->port_config.cdc_dma.data_format = AFE_LINEAR_PCM_DATA_PACKED_16BIT; rc = afe_send_cdc_dma_data_align(dai->id, dai_data->cdc_dma_data_align); if (rc) pr_debug("%s: afe send data alignment failed %d\n", __func__, rc); rc = afe_port_start(dai->id, &dai_data->port_config, dai_data->rate); if (rc < 0) Loading Loading @@ -12987,6 +12994,12 @@ static int msm_dai_q6_cdc_dma_dev_probe(struct platform_device *pdev) if (rc) dev_dbg(&pdev->dev, "island supported entry not found\n"); rc = of_property_read_u32(pdev->dev.of_node, "qcom,msm-cdc-dma-data-align", &dai_data->cdc_dma_data_align); if (rc) dev_dbg(&pdev->dev, "cdc dma data align supported entry not found\n"); dev_set_drvdata(&pdev->dev, dai_data); for (i = 0; i < ARRAY_SIZE(msm_dai_q6_cdc_dma_dai); i++) { Loading
dsp/q6afe.c +43 −0 Original line number Diff line number Diff line Loading @@ -2593,6 +2593,49 @@ static void afe_send_cal_spkr_prot_rx(int port_id) return; } /** * afe_send_cdc_dma_data_align - * for sending codec dma data alignment * * @port_id: AFE port id number */ int afe_send_cdc_dma_data_align(u16 port_id, u32 cdc_dma_data_align) { struct afe_param_id_cdc_dma_data_align data_align; struct param_hdr_v3 param_info; uint16_t port_index = 0; int ret = -EINVAL; memset(&data_align, 0, sizeof(data_align)); memset(¶m_info, 0, sizeof(param_info)); port_index = afe_get_port_index(port_id); if (port_index < 0 || port_index >= AFE_MAX_PORTS) { pr_err("%s: AFE port index[%d] invalid!\n", __func__, port_index); return -EINVAL; } data_align.cdc_dma_data_align = cdc_dma_data_align; pr_debug("%s: port_id %x, data_align %d\n", __func__, port_id, data_align.cdc_dma_data_align); param_info.module_id = AFE_MODULE_AUDIO_DEV_INTERFACE; param_info.instance_id = INSTANCE_ID_0; param_info.param_id = AFE_PARAM_ID_CODEC_DMA_DATA_ALIGN; param_info.param_size = sizeof(data_align); ret = q6afe_pack_and_set_param_in_band(port_id, q6audio_get_port_index(port_id), param_info, (u8 *) &data_align); if (ret) pr_err("%s: AFE cdc cdc data alignment for port 0x%x failed %d\n", __func__, port_id, ret); return ret; } EXPORT_SYMBOL(afe_send_cdc_dma_data_align); static int afe_send_hw_delay(u16 port_id, u32 rate) { struct audio_cal_hw_delay_entry delay_entry; Loading
include/dsp/apr_audio-v2.h +6 −0 Original line number Diff line number Diff line Loading @@ -3951,6 +3951,12 @@ struct afe_param_id_set_topology_cfg { u32 topology_id; } __packed; #define AFE_PARAM_ID_CODEC_DMA_DATA_ALIGN 0x000102EA struct afe_param_id_cdc_dma_data_align { uint32_t cdc_dma_data_align; } __packed; #define MAX_ABR_LEVELS 5 struct afe_bit_rate_level_map_t { Loading
include/dsp/q6afe-v2.h +1 −0 Original line number Diff line number Diff line Loading @@ -395,6 +395,7 @@ void afe_set_vad_cfg(u32 vad_enable, u32 preroll_config, u32 port_id); void afe_set_island_mode_cfg(u16 port_id, u32 enable_flag); void afe_get_island_mode_cfg(u16 port_id, u32 *enable_flag); int afe_send_cdc_dma_data_align(u16 port_id, u32 cdc_dma_data_align); int afe_port_start(u16 port_id, union afe_port_config *afe_config, u32 rate); int afe_set_tws_channel_mode(u32 foramt, u16 port_id, u32 channel_mode); Loading