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Commit 931dbd1b authored by Yuanfang Zhang's avatar Yuanfang Zhang Committed by Gerrit - the friendly Code Review server
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coresight-tmc: increase qdss pcie sw path throughput 



Increase throughput for qdss pcie sw path.

Change-Id: I4bb52e81d2617d8e83d0dcfe525cad2f6f5ca93a
Signed-off-by: default avatarYuanfang Zhang <quic_yuanfang@quicinc.com>
parent 29910cbf

drivers/hwtracing/coresight/coresight-tmc-etr.c

+3 −1
Original line number Diff line number Diff line
@@ -1129,9 +1129,11 @@ tmc_etr_setup_sysfs_buf(struct tmc_drvdata *drvdata) 
			&& drvdata->byte_cntr->sw_usb)

			new_buf = tmc_alloc_etr_buf(drvdata, TMC_ETR_SW_USB_BUF_SIZE,

					 0, cpu_to_node(0), NULL);

		else if (drvdata->out_mode == TMC_ETR_OUT_MODE_PCIE)

		else if (drvdata->out_mode == TMC_ETR_OUT_MODE_PCIE) {

			new_buf = tmc_alloc_etr_buf(drvdata, TMC_ETR_PCIE_MEM_SIZE,

					 0, cpu_to_node(0), NULL);

			drvdata->size = TMC_ETR_PCIE_MEM_SIZE;

		}

		else

			new_buf = tmc_alloc_etr_buf(drvdata, drvdata->size,

					 0, cpu_to_node(0), NULL);

drivers/hwtracing/coresight/coresight-tmc.h

+1 −1
Original line number Diff line number Diff line
@@ -104,7 +104,7 @@ 
#define TMC_ETR_BAM_PIPE_INDEX	0

#define TMC_ETR_BAM_NR_PIPES	2



#define TMC_ETR_PCIE_MEM_SIZE	0x400000

#define TMC_ETR_PCIE_MEM_SIZE	0x2000000



#define TMC_AUTH_NSID_MASK	GENMASK(1, 0)