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Commit 92fa4f4c authored by Kunihiko Hayashi's avatar Kunihiko Hayashi Committed by Masahiro Yamada
Browse files

ARM: dts: uniphier: add SPI node for UniPhier 32bit SoCs 



Add nodes of SPI controller for LD4, Pro4, sLD8, Pro5 and PXs2.

Signed-off-by: default avatarKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
parent dc0a2098

arch/arm/boot/dts/uniphier-ld4.dtsi

+11 −0
Original line number Diff line number Diff line
@@ -63,6 +63,17 @@ 
			cache-level = <2>;

		};



		spi: spi@54006000 {

			compatible = "socionext,uniphier-scssi";

			status = "disabled";

			reg = <0x54006000 0x100>;

			interrupts = <0 39 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_spi0>;

			clocks = <&peri_clk 11>;

			resets = <&peri_rst 11>;

		};



		serial0: serial@54006800 {

			compatible = "socionext,uniphier-uart";

			status = "disabled";

arch/arm/boot/dts/uniphier-pro4.dtsi

+11 −0
Original line number Diff line number Diff line
@@ -71,6 +71,17 @@ 
			cache-level = <2>;

		};



		spi0: spi@54006000 {

			compatible = "socionext,uniphier-scssi";

			status = "disabled";

			reg = <0x54006000 0x100>;

			interrupts = <0 39 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_spi0>;

			clocks = <&peri_clk 11>;

			resets = <&peri_rst 11>;

		};



		serial0: serial@54006800 {

			compatible = "socionext,uniphier-uart";

			status = "disabled";

arch/arm/boot/dts/uniphier-pro5.dtsi

+22 −0
Original line number Diff line number Diff line
@@ -156,6 +156,28 @@ 
			cache-level = <3>;

		};



		spi0: spi@54006000 {

			compatible = "socionext,uniphier-scssi";

			status = "disabled";

			reg = <0x54006000 0x100>;

			interrupts = <0 39 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_spi0>;

			clocks = <&peri_clk 11>;

			resets = <&peri_rst 11>;

		};



		spi1: spi@54006100 {

			compatible = "socionext,uniphier-scssi";

			status = "disabled";

			reg = <0x54006100 0x100>;

			interrupts = <0 216 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_spi1>;

			clocks = <&peri_clk 11>;

			resets = <&peri_rst 11>;

		};



		serial0: serial@54006800 {

			compatible = "socionext,uniphier-uart";

			status = "disabled";

arch/arm/boot/dts/uniphier-pxs2.dtsi

+22 −0
Original line number Diff line number Diff line
@@ -167,6 +167,28 @@ 
			cache-level = <2>;

		};



		spi0: spi@54006000 {

			compatible = "socionext,uniphier-scssi";

			status = "disabled";

			reg = <0x54006000 0x100>;

			interrupts = <0 39 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_spi0>;

			clocks = <&peri_clk 11>;

			resets = <&peri_rst 11>;

		};



		spi1: spi@54006100 {

			compatible = "socionext,uniphier-scssi";

			status = "disabled";

			reg = <0x54006100 0x100>;

			interrupts = <0 216 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_spi1>;

			clocks = <&peri_clk 11>;

			resets = <&peri_rst 11>;

		};



		serial0: serial@54006800 {

			compatible = "socionext,uniphier-uart";

			status = "disabled";

arch/arm/boot/dts/uniphier-sld8.dtsi

+11 −0
Original line number Diff line number Diff line
@@ -63,6 +63,17 @@ 
			cache-level = <2>;

		};



		spi: spi@54006000 {

			compatible = "socionext,uniphier-scssi";

			status = "disabled";

			reg = <0x54006000 0x100>;

			interrupts = <0 39 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_spi0>;

			clocks = <&peri_clk 11>;

			resets = <&peri_rst 11>;

		};



		serial0: serial@54006800 {

			compatible = "socionext,uniphier-uart";

			status = "disabled";