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Commit 92414f32 authored by Brett Creeley's avatar Brett Creeley Committed by Jeff Kirsher
Browse files

ice: Update comment regarding the ITR_GRAN_S 



Since the driver now hard codes the ITR granularity to 2 us in the
GLINT_CTL register the comment next to ITR_GRAN_S needs to be updated.

Signed-off-by: default avatarBrett Creeley <brett.creeley@intel.com>
Signed-off-by: default avatarAnirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Tested-by: default avatarAndrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 6c2f997a

drivers/net/ethernet/intel/ice/ice_txrx.h

+1 −1
Original line number Diff line number Diff line
@@ -128,7 +128,7 @@ enum ice_rx_dtype { 
#define ICE_ITR_DYNAMIC	0x8000  /* used as flag for itr_setting */

#define ITR_IS_DYNAMIC(setting) (!!((setting) & ICE_ITR_DYNAMIC))

#define ITR_TO_REG(setting)	((setting) & ~ICE_ITR_DYNAMIC)

#define ICE_ITR_GRAN_S		1	/* Assume ITR granularity is 2us */

#define ICE_ITR_GRAN_S		1	/* ITR granularity is always 2us */

#define ICE_ITR_GRAN_US		BIT(ICE_ITR_GRAN_S)

#define ICE_ITR_MASK		0x1FFE	/* ITR register value alignment mask */

#define ITR_REG_ALIGN(setting)	__ALIGN_MASK(setting, ~ICE_ITR_MASK)