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Commit 91f6c90c authored by Tony Lindgren's avatar Tony Lindgren
Browse files

Merge branch 'omap4_and_sdrc_2.6.27' of git://git.pwsan.com/linux-2.6 into omap-for-linus

parents 6e457bb0 a3fed9bc

arch/arm/mach-omap2/clock44xx_data.c

+876 −566

File changed.

Preview size limit exceeded, changes collapsed.

arch/arm/mach-omap2/cm-regbits-44xx.h

+670 −617

File changed.

Preview size limit exceeded, changes collapsed.

arch/arm/mach-omap2/cm44xx.h

+88 −2
Original line number Diff line number Diff line
@@ -195,6 +195,42 @@ 
#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET		0x0088

#define OMAP4430_CM1_ABE_WDT3_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0088)



/* CM1.RESTORE_CM1 register offsets */

#define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET		0x0000

#define OMAP4430_CM_CLKSEL_CORE_RESTORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0000)

#define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET	0x0004

#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0004)

#define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET	0x0008

#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0008)

#define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET	0x000c

#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x000c)

#define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET	0x0010

#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0010)

#define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET	0x0014

#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0014)

#define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET	0x0018

#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0018)

#define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET	0x001c

#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x001c)

#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET	0x0020

#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE	OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0020)

#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE_OFFSET	0x0024

#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE	OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0024)

#define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET	0x0028

#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0028)

#define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET	0x002c

#define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x002c)

#define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET	0x0030

#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0030)

#define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET	0x0034

#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0034)

#define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET		0x0038

#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0038)

#define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET	0x003c

#define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE	OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x003c)

#define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET		0x0040

#define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0040)



/* CM2 */



/* CM2.OCP_SOCKET_CM2 register offsets */
@@ -252,8 +288,6 @@ 
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0068)

#define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET		0x006c

#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x006c)

#define OMAP4_CM_EMU_OVERRIDE_DPLL_PER_OFFSET		0x0070

#define OMAP4430_CM_EMU_OVERRIDE_DPLL_PER		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0070)

#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET		0x0080

#define OMAP4430_CM_CLKMODE_DPLL_USB			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0080)

#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET			0x0084
@@ -296,6 +330,8 @@ 
#define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0030)

#define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET		0x0038

#define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0038)

#define OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET		0x0040

#define OMAP4430_CM_ALWON_USBPHY_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0040)



/* CM2.CORE_CM2 register offsets */

#define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET			0x0000
@@ -578,4 +614,54 @@ 
#define OMAP4430_CM_CEFUSE_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0000)

#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET		0x0020

#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0020)



/* CM2.RESTORE_CM2 register offsets */

#define OMAP4_CM_L3_1_CLKSTCTRL_RESTORE_OFFSET		0x0000

#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0000)

#define OMAP4_CM_L3_2_CLKSTCTRL_RESTORE_OFFSET		0x0004

#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0004)

#define OMAP4_CM_L4CFG_CLKSTCTRL_RESTORE_OFFSET		0x0008

#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0008)

#define OMAP4_CM_MEMIF_CLKSTCTRL_RESTORE_OFFSET		0x000c

#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x000c)

#define OMAP4_CM_L4PER_CLKSTCTRL_RESTORE_OFFSET		0x0010

#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0010)

#define OMAP4_CM_L3INIT_CLKSTCTRL_RESTORE_OFFSET	0x0014

#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0014)

#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_RESTORE_OFFSET	0x0018

#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE	OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0018)

#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE_OFFSET	0x001c

#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE	OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x001c)

#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE_OFFSET	0x0020

#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE	OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0020)

#define OMAP4_CM_CM2_PROFILING_CLKCTRL_RESTORE_OFFSET	0x0024

#define OMAP4430_CM_CM2_PROFILING_CLKCTRL_RESTORE	OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0024)

#define OMAP4_CM_D2D_STATICDEP_RESTORE_OFFSET		0x0028

#define OMAP4430_CM_D2D_STATICDEP_RESTORE		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0028)

#define OMAP4_CM_L3_1_DYNAMICDEP_RESTORE_OFFSET		0x002c

#define OMAP4430_CM_L3_1_DYNAMICDEP_RESTORE		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x002c)

#define OMAP4_CM_L3_2_DYNAMICDEP_RESTORE_OFFSET		0x0030

#define OMAP4430_CM_L3_2_DYNAMICDEP_RESTORE		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0030)

#define OMAP4_CM_D2D_DYNAMICDEP_RESTORE_OFFSET		0x0034

#define OMAP4430_CM_D2D_DYNAMICDEP_RESTORE		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0034)

#define OMAP4_CM_L4CFG_DYNAMICDEP_RESTORE_OFFSET	0x0038

#define OMAP4430_CM_L4CFG_DYNAMICDEP_RESTORE		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0038)

#define OMAP4_CM_L4PER_DYNAMICDEP_RESTORE_OFFSET	0x003c

#define OMAP4430_CM_L4PER_DYNAMICDEP_RESTORE		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x003c)

#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_RESTORE_OFFSET	0x0040

#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0040)

#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_RESTORE_OFFSET	0x0044

#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0044)

#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_RESTORE_OFFSET	0x0048

#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0048)

#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_RESTORE_OFFSET	0x004c

#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x004c)

#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_RESTORE_OFFSET	0x0050

#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0050)

#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE_OFFSET	0x0054

#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE	OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0054)

#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE_OFFSET	0x0058

#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE	OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0058)

#define OMAP4_CM_SDMA_STATICDEP_RESTORE_OFFSET		0x005c

#define OMAP4430_CM_SDMA_STATICDEP_RESTORE		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x005c)

#endif

arch/arm/mach-omap2/control.c

+25 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 
#include "sdrc.h"



static void __iomem *omap2_ctrl_base;

static void __iomem *omap4_ctrl_pad_base;



#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)

struct omap3_scratchpad {
@@ -137,6 +138,7 @@ static struct omap3_control_regs control_context; 
#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */



#define OMAP_CTRL_REGADDR(reg)		(omap2_ctrl_base + (reg))

#define OMAP4_CTRL_PAD_REGADDR(reg)	(omap4_ctrl_pad_base + (reg))



void __init omap2_set_globals_control(struct omap_globals *omap2_globals)

{
@@ -145,6 +147,12 @@ void __init omap2_set_globals_control(struct omap_globals *omap2_globals) 
		omap2_ctrl_base = ioremap(omap2_globals->ctrl, SZ_4K);

		WARN_ON(!omap2_ctrl_base);

	}



	/* Static mapping, never released */

	if (omap2_globals->ctrl_pad) {

		omap4_ctrl_pad_base = ioremap(omap2_globals->ctrl_pad, SZ_4K);

		WARN_ON(!omap4_ctrl_pad_base);

	}

}



void __iomem *omap_ctrl_base_get(void)
@@ -182,6 +190,23 @@ void omap_ctrl_writel(u32 val, u16 offset) 
	__raw_writel(val, OMAP_CTRL_REGADDR(offset));

}



/*

 * On OMAP4 control pad are not addressable from control

 * core base. So the common omap_ctrl_read/write APIs breaks

 * Hence export separate APIs to manage the omap4 pad control

 * registers. This APIs will work only for OMAP4

 */



u32 omap4_ctrl_pad_readl(u16 offset)

{

	return __raw_readl(OMAP4_CTRL_PAD_REGADDR(offset));

}



void omap4_ctrl_pad_writel(u32 val, u16 offset)

{

	__raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset));

}



#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)

/*

 * Clears the scratchpad contents in case of cold boot-

arch/arm/mach-omap2/hsmmc.c

+36 −31
Original line number Diff line number Diff line
@@ -135,10 +135,11 @@ static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot, 
	 *

	 * FIXME handle VMMC1A as needed ...

	 */

	reg = omap_ctrl_readl(control_pbias_offset);

	reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ |

					OMAP4_USBC1_ICUSB_PWRDNZ);

	omap_ctrl_writel(reg, control_pbias_offset);

	reg = omap4_ctrl_pad_readl(control_pbias_offset);

	reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |

		OMAP4_MMC1_PWRDNZ_MASK |

		OMAP4_USBC1_ICUSB_PWRDNZ_MASK);

	omap4_ctrl_pad_writel(reg, control_pbias_offset);

}



static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
@@ -147,30 +148,33 @@ static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot, 
	u32 reg;



	if (power_on) {

		reg = omap_ctrl_readl(control_pbias_offset);

		reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ;

		reg = omap4_ctrl_pad_readl(control_pbias_offset);

		reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK;

		if ((1 << vdd) <= MMC_VDD_165_195)

			reg &= ~OMAP4_MMC1_PBIASLITE_VMODE;

			reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK;

		else

			reg |= OMAP4_MMC1_PBIASLITE_VMODE;

		reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ |

						OMAP4_USBC1_ICUSB_PWRDNZ);

		omap_ctrl_writel(reg, control_pbias_offset);

			reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;

		reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |

			OMAP4_MMC1_PWRDNZ_MASK |

			OMAP4_USBC1_ICUSB_PWRDNZ_MASK);

		omap4_ctrl_pad_writel(reg, control_pbias_offset);

		/* 4 microsec delay for comparator to generate an error*/

		udelay(4);

		reg = omap_ctrl_readl(control_pbias_offset);

		if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR) {

		reg = omap4_ctrl_pad_readl(control_pbias_offset);

		if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {

			pr_err("Pbias Voltage is not same as LDO\n");

			/* Caution : On VMODE_ERROR Power Down MMC IO */

			reg &= ~(OMAP4_MMC1_PWRDNZ | OMAP4_USBC1_ICUSB_PWRDNZ);

			omap_ctrl_writel(reg, control_pbias_offset);

			reg &= ~(OMAP4_MMC1_PWRDNZ_MASK |

				OMAP4_USBC1_ICUSB_PWRDNZ_MASK);

			omap4_ctrl_pad_writel(reg, control_pbias_offset);

		}

	} else {

		reg = omap_ctrl_readl(control_pbias_offset);

		 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ |

			OMAP4_MMC1_PBIASLITE_VMODE | OMAP4_MMC1_PWRDNZ |

			OMAP4_USBC1_ICUSB_PWRDNZ);

		omap_ctrl_writel(reg, control_pbias_offset);

		reg = omap4_ctrl_pad_readl(control_pbias_offset);

		reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |

			OMAP4_MMC1_PWRDNZ_MASK |

			OMAP4_MMC1_PBIASLITE_VMODE_MASK |

			OMAP4_USBC1_ICUSB_PWRDNZ_MASK);

		omap4_ctrl_pad_writel(reg, control_pbias_offset);

	}

}
@@ -218,17 +222,18 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) 
			control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;

		}

	} else {

		control_pbias_offset = OMAP44XX_CONTROL_PBIAS_LITE;

		control_mmc1 = OMAP44XX_CONTROL_MMC1;

		reg = omap_ctrl_readl(control_mmc1);

		reg |= (OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 |

			OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1);

		reg &= ~(OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 |

			OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3);

		reg |= (OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL |

			OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL |

			OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL);

		omap_ctrl_writel(reg, control_mmc1);

		control_pbias_offset =

			OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;

		control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;

		reg = omap4_ctrl_pad_readl(control_mmc1);

		reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |

			OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);

		reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |

			OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);

		reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK|

			OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |

			OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);

		omap4_ctrl_pad_writel(reg, control_mmc1);

	}



	for (c = controllers; c->mmc; c++) {