Loading fw/htt.h +2 −0 Original line number Diff line number Diff line Loading @@ -669,6 +669,8 @@ typedef enum { HTT_STATS_TX_SELFGEN_BE_ERR_STATS_TAG = 137, /* htt_tx_selfgen_be_err_stats_tlv */ HTT_STATS_TX_SELFGEN_BE_STATS_TAG = 138, /* htt_tx_selfgen_be_stats_tlv */ HTT_STATS_TX_SELFGEN_BE_SCHED_STATUS_STATS_TAG = 139, /* htt_tx_selfgen_be_sched_status_stats_tlv */ HTT_STATS_TX_PDEV_BE_UL_MU_MIMO_STATS_TAG = 140, /* htt_tx_pdev_be_ul_mu_mimo_sch_stats_tlv */ HTT_STATS_RX_PDEV_BE_UL_MIMO_USER_STATS_TAG = 141, /* htt_rx_pdev_be_ul_mimo_user_stats_tlv */ HTT_STATS_MAX_TAG, Loading fw/htt_stats.h +18 −0 Original line number Diff line number Diff line Loading @@ -2454,6 +2454,14 @@ typedef struct { A_UINT32 ax_ul_mu_mimo_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; } htt_tx_pdev_ul_mu_mimo_sch_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; /* Represents the count for 11BE UL MU MIMO sequences with Basic Triggers */ A_UINT32 be_ul_mu_mimo_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; /* Represents the count for 11BE UL MU MIMO sequences with BRP Triggers */ A_UINT32 be_ul_mu_mimo_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; } htt_tx_pdev_be_ul_mu_mimo_sch_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; A_UINT32 mu_mimo_mpdus_queued_usr; /* 11AC DL MU MIMO number of mpdus queued to HW, per user */ Loading Loading @@ -4234,6 +4242,16 @@ typedef struct { A_UINT32 rx_ulmumimo_mpdu_fail; /* mpdu level */ } htt_rx_pdev_ul_mimo_user_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; A_UINT32 user_index; A_UINT32 be_rx_ulmumimo_non_data_ppdu; /* ppdu level */ A_UINT32 be_rx_ulmumimo_data_ppdu; /* ppdu level */ A_UINT32 be_rx_ulmumimo_mpdu_ok; /* mpdu level */ A_UINT32 be_rx_ulmumimo_mpdu_fail; /* mpdu level */ } htt_rx_pdev_be_ul_mimo_user_stats_tlv; /* == RX PDEV/SOC STATS == */ typedef struct { Loading Loading
fw/htt.h +2 −0 Original line number Diff line number Diff line Loading @@ -669,6 +669,8 @@ typedef enum { HTT_STATS_TX_SELFGEN_BE_ERR_STATS_TAG = 137, /* htt_tx_selfgen_be_err_stats_tlv */ HTT_STATS_TX_SELFGEN_BE_STATS_TAG = 138, /* htt_tx_selfgen_be_stats_tlv */ HTT_STATS_TX_SELFGEN_BE_SCHED_STATUS_STATS_TAG = 139, /* htt_tx_selfgen_be_sched_status_stats_tlv */ HTT_STATS_TX_PDEV_BE_UL_MU_MIMO_STATS_TAG = 140, /* htt_tx_pdev_be_ul_mu_mimo_sch_stats_tlv */ HTT_STATS_RX_PDEV_BE_UL_MIMO_USER_STATS_TAG = 141, /* htt_rx_pdev_be_ul_mimo_user_stats_tlv */ HTT_STATS_MAX_TAG, Loading
fw/htt_stats.h +18 −0 Original line number Diff line number Diff line Loading @@ -2454,6 +2454,14 @@ typedef struct { A_UINT32 ax_ul_mu_mimo_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; } htt_tx_pdev_ul_mu_mimo_sch_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; /* Represents the count for 11BE UL MU MIMO sequences with Basic Triggers */ A_UINT32 be_ul_mu_mimo_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; /* Represents the count for 11BE UL MU MIMO sequences with BRP Triggers */ A_UINT32 be_ul_mu_mimo_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; } htt_tx_pdev_be_ul_mu_mimo_sch_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; A_UINT32 mu_mimo_mpdus_queued_usr; /* 11AC DL MU MIMO number of mpdus queued to HW, per user */ Loading Loading @@ -4234,6 +4242,16 @@ typedef struct { A_UINT32 rx_ulmumimo_mpdu_fail; /* mpdu level */ } htt_rx_pdev_ul_mimo_user_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; A_UINT32 user_index; A_UINT32 be_rx_ulmumimo_non_data_ppdu; /* ppdu level */ A_UINT32 be_rx_ulmumimo_data_ppdu; /* ppdu level */ A_UINT32 be_rx_ulmumimo_mpdu_ok; /* mpdu level */ A_UINT32 be_rx_ulmumimo_mpdu_fail; /* mpdu level */ } htt_rx_pdev_be_ul_mimo_user_stats_tlv; /* == RX PDEV/SOC STATS == */ typedef struct { Loading