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Commit 90e83e53 authored by Ander Conselvan de Oliveira's avatar Ander Conselvan de Oliveira
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drm/i915: Wait for vblank in i9xx_disable_crtc() for gen 2 only 



The wait for other gens was added in commit 564ed191 ("drm/i915:
gmch: fix stuck primary plane due to memory self-refresh mode") since
that's necessary when disabling cxsr. However, cxsr disabling was later
moved to intel_pre_disable_primary() in commit 87d4300a ("drm/i915:
Move intel_(pre_disable/post_enable)_primary to intel_display.c, and use
it there.") and that function got its own vblank wait for cxsr in commit
262cd2e1 ("drm/i915: CHV DDR DVFS support and another watermark
rewrite"). So remove the extra vblank wait from i9xx_crtc_distable().

Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
Signed-off-by: default avatarAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1458634284-6080-1-git-send-email-ander.conselvan.de.oliveira@intel.com
parent 2dc10cd8

drivers/gpu/drm/i915/intel_display.c

+2 −3
Original line number Diff line number Diff line
@@ -6212,9 +6212,8 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc) 
	/*

	 * On gen2 planes are double buffered but the pipe isn't, so we must

	 * wait for planes to fully turn off before disabling the pipe.

	 * We also need to wait on all gmch platforms because of the

	 * self-refresh mode constraint explained above.

	 */

	if (IS_GEN2(dev))

		intel_wait_for_vblank(dev, pipe);



	for_each_encoder_on_crtc(dev, crtc, encoder)