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Commit 90e66dd9 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'for-linus' of git://linux-c6x.org/git/projects/linux-c6x-upstreaming 

Pull C6X changes from Mark Salter:

  - remove use of legacy irqs which really wasn't needed
  - add support for C66x SoC on EVMC6678 board
  - clean up compiler warning

* tag 'for-linus' of git://linux-c6x.org/git/projects/linux-c6x-upstreaming:
  C6X: clean up compiler warning
  C6X: add basic support for TMS320C6678 SoC
  C6X: remove dependence on legacy IRQs
  C6X: remove megamod-pic requirement on direct-mapped core pic
parents f0a08fcb b9b8722d

arch/c6x/boot/dts/evmc6678.dts

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+83 −0
Original line number Diff line number Diff line 
/*

 * arch/c6x/boot/dts/evmc6678.dts

 *

 * EVMC6678 Evaluation Platform For TMS320C6678

 *

 * Copyright (C) 2012 Texas Instruments Incorporated

 *

 * Author: Ken Cox <jkc@redhat.com>

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License

 * as published by the Free Software Foundation; either version 2

 * of the License, or (at your option) any later version.

 *

 */



/dts-v1/;



/include/ "tms320c6678.dtsi"



/ {

	model = "Advantech EVMC6678";

	compatible = "advantech,evmc6678";



	chosen {

		bootargs = "root=/dev/nfs ip=dhcp rw";

	};



	memory {

		device_type = "memory";

		reg = <0x80000000 0x20000000>;

	};



	soc {

		megamod_pic: interrupt-controller@1800000 {

		       interrupts = < 12 13 14 15 >;

		};



		timer8: timer@2280000 {

			interrupt-parent = <&megamod_pic>;

			interrupts = < 66 >;

		};



		timer9: timer@2290000 {

			interrupt-parent = <&megamod_pic>;

			interrupts = < 68 >;

		};



		timer10: timer@22A0000 {

			interrupt-parent = <&megamod_pic>;

			interrupts = < 70 >;

		};



		timer11: timer@22B0000 {

			interrupt-parent = <&megamod_pic>;

			interrupts = < 72 >;

		};



		timer12: timer@22C0000 {

			interrupt-parent = <&megamod_pic>;

			interrupts = < 74 >;

		};



		timer13: timer@22D0000 {

			interrupt-parent = <&megamod_pic>;

			interrupts = < 76 >;

		};



		timer14: timer@22E0000 {

			interrupt-parent = <&megamod_pic>;

			interrupts = < 78 >;

		};



		timer15: timer@22F0000 {

			interrupt-parent = <&megamod_pic>;

			interrupts = < 80 >;

		};



		clock-controller@2310000 {

			clock-frequency = <100000000>;

		};

	};

};

arch/c6x/boot/dts/tms320c6678.dtsi

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+146 −0
Original line number Diff line number Diff line 


/ {

	#address-cells = <1>;

	#size-cells = <1>;



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu@0 {

			device_type = "cpu";

			reg = <0>;

			model = "ti,c66x";

		};

		cpu@1 {

			device_type = "cpu";

			reg = <1>;

			model = "ti,c66x";

		};

		cpu@2 {

			device_type = "cpu";

			reg = <2>;

			model = "ti,c66x";

		};

		cpu@3 {

			device_type = "cpu";

			reg = <3>;

			model = "ti,c66x";

		};

		cpu@4 {

			device_type = "cpu";

			reg = <4>;

			model = "ti,c66x";

		};

		cpu@5 {

			device_type = "cpu";

			reg = <5>;

			model = "ti,c66x";

		};

		cpu@6 {

			device_type = "cpu";

			reg = <6>;

			model = "ti,c66x";

		};

		cpu@7 {

			device_type = "cpu";

			reg = <7>;

			model = "ti,c66x";

		};

	};



	soc {

		compatible = "simple-bus";

		model = "tms320c6678";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		core_pic: interrupt-controller {

			compatible = "ti,c64x+core-pic";

			interrupt-controller;

			#interrupt-cells = <1>;

		};



		megamod_pic: interrupt-controller@1800000 {

		       compatible = "ti,c64x+megamod-pic";

		       interrupt-controller;

		       #interrupt-cells = <1>;

		       reg = <0x1800000 0x1000>;

		       interrupt-parent = <&core_pic>;

		};



		cache-controller@1840000 {

			compatible = "ti,c64x+cache";

			reg = <0x01840000 0x8400>;

		};



		timer8: timer@2280000 {

			compatible = "ti,c64x+timer64";

			ti,core-mask = < 0x01 >;

			reg = <0x2280000 0x40>;

		};



		timer9: timer@2290000 {

			compatible = "ti,c64x+timer64";

			ti,core-mask = < 0x02 >;

			reg = <0x2290000 0x40>;

		};



		timer10: timer@22A0000 {

			compatible = "ti,c64x+timer64";

			ti,core-mask = < 0x04 >;

			reg = <0x22A0000 0x40>;

		};



		timer11: timer@22B0000 {

			compatible = "ti,c64x+timer64";

			ti,core-mask = < 0x08 >;

			reg = <0x22B0000 0x40>;

		};



		timer12: timer@22C0000 {

			compatible = "ti,c64x+timer64";

			ti,core-mask = < 0x10 >;

			reg = <0x22C0000 0x40>;

		};



		timer13: timer@22D0000 {

			compatible = "ti,c64x+timer64";

			ti,core-mask = < 0x20 >;

			reg = <0x22D0000 0x40>;

		};



		timer14: timer@22E0000 {

			compatible = "ti,c64x+timer64";

			ti,core-mask = < 0x40 >;

			reg = <0x22E0000 0x40>;

		};



		timer15: timer@22F0000 {

			compatible = "ti,c64x+timer64";

			ti,core-mask = < 0x80 >;

			reg = <0x22F0000 0x40>;

		};



		clock-controller@2310000 {

			compatible = "ti,c6678-pll", "ti,c64x+pll";

			reg = <0x02310000 0x200>;

			ti,c64x+pll-bypass-delay = <200>;

			ti,c64x+pll-reset-delay = <12000>;

			ti,c64x+pll-lock-delay = <80000>;

		};



		device-state-controller@2620000 {

			compatible = "ti,c64x+dscr";

			reg = <0x02620000 0x1000>;



			ti,dscr-devstat = <0x20>;

			ti,dscr-silicon-rev = <0x18 28 0xf>;



			ti,dscr-mac-fuse-regs = <0x110 1 2 3 4

						 0x114 5 6 0 0>;



		};

	};

};

arch/c6x/configs/evmc6678_defconfig

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+42 −0
Original line number Diff line number Diff line 
CONFIG_SOC_TMS320C6678=y

CONFIG_EXPERIMENTAL=y

# CONFIG_LOCALVERSION_AUTO is not set

CONFIG_SYSVIPC=y

CONFIG_SPARSE_IRQ=y

CONFIG_LOG_BUF_SHIFT=14

CONFIG_NAMESPACES=y

# CONFIG_UTS_NS is not set

# CONFIG_USER_NS is not set

# CONFIG_PID_NS is not set

CONFIG_BLK_DEV_INITRD=y

CONFIG_CC_OPTIMIZE_FOR_SIZE=y

CONFIG_EXPERT=y

# CONFIG_FUTEX is not set

# CONFIG_SLUB_DEBUG is not set

CONFIG_MODULES=y

CONFIG_MODULE_FORCE_LOAD=y

CONFIG_MODULE_UNLOAD=y

CONFIG_MODULE_FORCE_UNLOAD=y

CONFIG_CMDLINE_BOOL=y

CONFIG_CMDLINE=""

# CONFIG_CMDLINE_FORCE is not set

CONFIG_BOARD_EVM6678=y

CONFIG_NO_HZ=y

CONFIG_HIGH_RES_TIMERS=y

CONFIG_BLK_DEV_LOOP=y

CONFIG_BLK_DEV_RAM=y

CONFIG_BLK_DEV_RAM_COUNT=2

CONFIG_BLK_DEV_RAM_SIZE=17000

CONFIG_MISC_DEVICES=y

# CONFIG_INPUT is not set

# CONFIG_SERIO is not set

# CONFIG_VT is not set

# CONFIG_HW_RANDOM is not set

# CONFIG_HWMON is not set

# CONFIG_USB_SUPPORT is not set

# CONFIG_IOMMU_SUPPORT is not set

# CONFIG_MISC_FILESYSTEMS is not set

CONFIG_CRC16=y

# CONFIG_ENABLE_MUST_CHECK is not set

# CONFIG_SCHED_DEBUG is not set

# CONFIG_DEBUG_BUGVERBOSE is not set

arch/c6x/include/asm/irq.h

+0 −2
Original line number Diff line number Diff line
@@ -34,8 +34,6 @@ 
 */

#define NR_PRIORITY_IRQS 16



#define NR_IRQS_LEGACY	NR_PRIORITY_IRQS



/* Total number of virq in the platform */

#define NR_IRQS		256

arch/c6x/kernel/irq.c

+10 −11
Original line number Diff line number Diff line 
/*

 *  Copyright (C) 2011 Texas Instruments Incorporated

 *  Copyright (C) 2011-2012 Texas Instruments Incorporated

 *

 *  This borrows heavily from powerpc version, which is:

 *
@@ -35,9 +35,7 @@ static DEFINE_RAW_SPINLOCK(core_irq_lock); 


static void mask_core_irq(struct irq_data *data)

{

	unsigned int prio = data->irq;



	BUG_ON(prio < 4 || prio >= NR_PRIORITY_IRQS);

	unsigned int prio = data->hwirq;



	raw_spin_lock(&core_irq_lock);

	and_creg(IER, ~(1 << prio));
@@ -46,7 +44,7 @@ static void mask_core_irq(struct irq_data *data) 


static void unmask_core_irq(struct irq_data *data)

{

	unsigned int prio = data->irq;

	unsigned int prio = data->hwirq;



	raw_spin_lock(&core_irq_lock);

	or_creg(IER, 1 << prio);
@@ -59,15 +57,15 @@ static struct irq_chip core_chip = { 
	.irq_unmask	= unmask_core_irq,

};



static int prio_to_virq[NR_PRIORITY_IRQS];



asmlinkage void c6x_do_IRQ(unsigned int prio, struct pt_regs *regs)

{

	struct pt_regs *old_regs = set_irq_regs(regs);



	irq_enter();



	BUG_ON(prio < 4 || prio >= NR_PRIORITY_IRQS);



	generic_handle_irq(prio);

	generic_handle_irq(prio_to_virq[prio]);



	irq_exit();
@@ -82,6 +80,8 @@ static int core_domain_map(struct irq_domain *h, unsigned int virq, 
	if (hw < 4 || hw >= NR_PRIORITY_IRQS)

		return -EINVAL;



	prio_to_virq[hw] = virq;



	irq_set_status_flags(virq, IRQ_LEVEL);

	irq_set_chip_and_handler(virq, &core_chip, handle_level_irq);

	return 0;
@@ -102,9 +102,8 @@ void __init init_IRQ(void) 
	np = of_find_compatible_node(NULL, NULL, "ti,c64x+core-pic");

	if (np != NULL) {

		/* create the core host */

		core_domain = irq_domain_add_legacy(np, NR_PRIORITY_IRQS,

						    0, 0, &core_domain_ops,

						    NULL);

		core_domain = irq_domain_add_linear(np, NR_PRIORITY_IRQS,

						    &core_domain_ops, NULL);

		if (core_domain)

			irq_set_default_host(core_domain);

		of_node_put(np);