CSR: Keep qdss clk being on for msr register before msr_reset

Swao msr registers' value will be reset to 0 when qdss clock is off.
Enable the qdss clock before set the msr register value and disable
the qdss clock after msr rest. It will make sure that the msr register
value won't be reset during tpdm enabled.

Change-Id: I79a26c47e7c5db88cf67a1b88bc9b2046c87b78e
Signed-off-by: Mao Jinlong <jinlmao@codeaurora.org>