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Commit 90c1e3c2 authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt Committed by Michael Ellerman
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powerpc/mm/radix: Update ERAT flushes when invalidating TLB 



Three tiny changes to the ERAT flushing logic: First don't make
it depend on DD1. It hasn't been decided yet but we might run
DD2 in a mode that also requires explicit flushes for performance
reasons so make it unconditional. We also add a missing isync, and
finally remove the flush from _tlbiel_va as it is only necessary
for congruence-class invalidations (PID, LPID and full TLB), not
targetted invalidations.

Fixes: 96ed1fe5 ("powerpc/mm/radix: Invalidate ERAT on tlbiel for POWER9 DD1")
Cc: stable@vger.kernel.org # v4.9+
Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent d7df2443

arch/powerpc/mm/tlb-radix.c

+1 −5
Original line number Diff line number Diff line
@@ -50,9 +50,7 @@ static inline void _tlbiel_pid(unsigned long pid, unsigned long ric) 
	for (set = 0; set < POWER9_TLB_SETS_RADIX ; set++) {

		__tlbiel_pid(pid, set, ric);

	}

	if (cpu_has_feature(CPU_FTR_POWER9_DD1))

		asm volatile(PPC_INVALIDATE_ERAT : : :"memory");

	return;

	asm volatile(PPC_INVALIDATE_ERAT "; isync" : : :"memory");

}



static inline void _tlbie_pid(unsigned long pid, unsigned long ric)
@@ -85,8 +83,6 @@ static inline void _tlbiel_va(unsigned long va, unsigned long pid, 
	asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)

		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");

	asm volatile("ptesync": : :"memory");

	if (cpu_has_feature(CPU_FTR_POWER9_DD1))

		asm volatile(PPC_INVALIDATE_ERAT : : :"memory");

}



static inline void _tlbie_va(unsigned long va, unsigned long pid,