Loading qcom/lahaina.dtsi +9 −0 Original line number Diff line number Diff line Loading @@ -463,6 +463,15 @@ }; }; dcc: dcc_v2@117f000 { compatible = "qcom,dcc-v2"; reg = <0x117f000 0x1000>, <0x1112000 0x6000>; reg-names = "dcc-base", "dcc-ram-base"; dcc-ram-offset = <0x12000>; }; cpu_pmu: cpu-pmu { compatible = "arm,armv8-pmuv3"; qcom,irq-is-percpu; Loading Loading
qcom/lahaina.dtsi +9 −0 Original line number Diff line number Diff line Loading @@ -463,6 +463,15 @@ }; }; dcc: dcc_v2@117f000 { compatible = "qcom,dcc-v2"; reg = <0x117f000 0x1000>, <0x1112000 0x6000>; reg-names = "dcc-base", "dcc-ram-base"; dcc-ram-offset = <0x12000>; }; cpu_pmu: cpu-pmu { compatible = "arm,armv8-pmuv3"; qcom,irq-is-percpu; Loading