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Commit 909a0873 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "dmaengine: gpi: Add support for 32-bit kernel"

parents e3225c64 f73e0943

drivers/dma/qcom/gpi.c

+4 −4
Original line number Diff line number Diff line
@@ -1843,12 +1843,12 @@ static int gpi_alloc_chan(struct gpii_chan *gpii_chan, bool send_alloc_cmd) 
		{

			gpii_chan->ch_cntxt_base_reg,

			CNTXT_3_RING_BASE_MSB,

			(u32)(ring->phys_addr >> 32),

			MSM_GPI_RING_PHYS_ADDR_UPPER(ring->phys_addr),

		},

		{ /* program MSB of DB register with ring base */

			gpii_chan->ch_cntxt_db_reg,

			CNTXT_5_RING_RP_MSB - CNTXT_4_RING_RP_LSB,

			(u32)(ring->phys_addr >> 32),

			MSM_GPI_RING_PHYS_ADDR_UPPER(ring->phys_addr),

		},

		{

			gpii->regs,
@@ -1937,13 +1937,13 @@ static int gpi_alloc_ev_chan(struct gpii *gpii) 
		{

			gpii->ev_cntxt_base_reg,

			CNTXT_3_RING_BASE_MSB,

			(u32)(ring->phys_addr >> 32),

			MSM_GPI_RING_PHYS_ADDR_UPPER(ring->phys_addr),

		},

		{

			/* program db msg with ring base msb */

			gpii->ev_cntxt_db_reg,

			CNTXT_5_RING_RP_MSB - CNTXT_4_RING_RP_LSB,

			(u32)(ring->phys_addr >> 32),

			MSM_GPI_RING_PHYS_ADDR_UPPER(ring->phys_addr),

		},

		{

			gpii->ev_cntxt_base_reg,

include/linux/msm_gpi.h

+22 −0
Original line number Diff line number Diff line
@@ -28,8 +28,14 @@ enum msm_gpi_tre_type { 
#define MSM_GPI_TRE_TYPE(tre) ((tre->dword[3] >> 16) & 0xFF)



/* DMA w. Buffer TRE */

#ifdef CONFIG_ARM64

#define MSM_GPI_DMA_W_BUFFER_TRE_DWORD0(ptr) ((u32)ptr)

#define MSM_GPI_DMA_W_BUFFER_TRE_DWORD1(ptr) ((u32)(ptr >> 32))

#else

#define MSM_GPI_DMA_W_BUFFER_TRE_DWORD0(ptr) (ptr)

#define MSM_GPI_DMA_W_BUFFER_TRE_DWORD1(ptr) 0

#endif



#define MSM_GPI_DMA_W_BUFFER_TRE_DWORD2(length) (length & 0xFFFFFF)

#define MSM_GPI_DMA_W_BUFFER_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) \

	((0x1 << 20) | (0x0 << 16) | (link_rx << 11) | (bei << 10) | \
@@ -50,16 +56,26 @@ enum msm_gpi_tre_type { 
#define MSM_GPI_DMA_IMMEDIATE_TRE_GET_LEN(tre) (tre->dword[2] & 0xF)



/* DMA w. Scatter/Gather List TRE */

#ifdef CONFIG_ARM64

#define MSM_GPI_SG_LIST_TRE_DWORD0(ptr) ((u32)ptr)

#define MSM_GPI_SG_LIST_TRE_DWORD1(ptr) ((u32)(ptr >> 32))

#else

#define MSM_GPI_SG_LIST_TRE_DWORD0(ptr) (ptr)

#define MSM_GPI_SG_LIST_TRE_DWORD1(ptr) 0

#endif

#define MSM_GPI_SG_LIST_TRE_DWORD2(length) (length & 0xFFFF)

#define MSM_GPI_SG_LIST_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) ((0x1 << 20) \

	| (0x2 << 16) | (link_rx << 11) | (bei << 10) | (ieot << 9) | \

	(ieob << 8) | ch)



/* SG Element */

#ifdef CONFIG_ARM64

#define MSM_GPI_SG_ELEMENT_DWORD0(ptr) ((u32)ptr)

#define MSM_GPI_SG_ELEMENT_DWORD1(ptr) ((u32)(ptr >> 32))

#else

#define MSM_GPI_SG_ELEMENT_DWORD0(ptr) (ptr)

#define MSM_GPI_SG_ELEMENT_DWORD1(ptr) 0

#endif

#define MSM_GSI_SG_ELEMENT_DWORD2(length) (length & 0xFFFFF)

#define MSM_GSI_SG_ELEMENT_DWORD3 (0)
@@ -139,6 +155,12 @@ enum msm_gpi_tre_type { 
	((0x2 << 20) | (0x2 << 16) | (link_rx << 11) | (bei << 10) | \

	(ieot << 9) | (ieob << 8) | ch)



#ifdef CONFIG_ARM64

#define MSM_GPI_RING_PHYS_ADDR_UPPER(ptr) ((u32)(ptr >> 32))

#else

#define MSM_GPI_RING_PHYS_ADDR_UPPER(ptr) 0

#endif



/* cmds to perform by using dmaengine_slave_config() */

enum msm_gpi_ctrl_cmd {

	MSM_GPI_INIT,