Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 908fd508 authored by Shirley Her (SC)'s avatar Shirley Her (SC) Committed by Ulf Hansson
Browse files

mmc: sdhci-pci-o2micro: Move functions in preparation to fix DLL lock phase shift issue 



Move functions in preparation to fix DLL lock phase shift issue

Signed-off-by: default avatarShirley Her <shirley.her@bayhubtech.com>
Acked-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 9674bab4

drivers/mmc/host/sdhci-pci-o2micro.c

+94 −93
Original line number Diff line number Diff line
@@ -58,6 +58,100 @@ 


#define O2_SD_DETECT_SETTING 0x324



static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host)

{

	ktime_t timeout;

	u32 scratch32;



	/* Wait max 50 ms */

	timeout = ktime_add_ms(ktime_get(), 50);

	while (1) {

		bool timedout = ktime_after(ktime_get(), timeout);



		scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE);

		if ((scratch32 & SDHCI_CARD_PRESENT) >> SDHCI_CARD_PRES_SHIFT

		    == (scratch32 & SDHCI_CD_LVL) >> SDHCI_CD_LVL_SHIFT)

			break;



		if (timedout) {

			pr_err("%s: Card Detect debounce never finished.\n",

			       mmc_hostname(host->mmc));

			sdhci_dumpregs(host);

			return;

		}

		udelay(10);

	}

}



static void sdhci_o2_enable_internal_clock(struct sdhci_host *host)

{

	ktime_t timeout;

	u16 scratch;

	u32 scratch32;



	/* PLL software reset */

	scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);

	scratch32 |= O2_PLL_SOFT_RESET;

	sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);

	udelay(1);

	scratch32 &= ~(O2_PLL_SOFT_RESET);

	sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);



	/* PLL force active */

	scratch32 |= O2_PLL_FORCE_ACTIVE;

	sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);



	/* Wait max 20 ms */

	timeout = ktime_add_ms(ktime_get(), 20);

	while (1) {

		bool timedout = ktime_after(ktime_get(), timeout);



		scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1);

		if (scratch & O2_PLL_LOCK_STATUS)

			break;

		if (timedout) {

			pr_err("%s: Internal clock never stabilised.\n",

			       mmc_hostname(host->mmc));

			sdhci_dumpregs(host);

			goto out;

		}

		udelay(10);

	}



	/* Wait for card detect finish */

	udelay(1);

	sdhci_o2_wait_card_detect_stable(host);



out:

	/* Cancel PLL force active */

	scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);

	scratch32 &= ~O2_PLL_FORCE_ACTIVE;

	sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);

}



static int sdhci_o2_get_cd(struct mmc_host *mmc)

{

	struct sdhci_host *host = mmc_priv(mmc);



	sdhci_o2_enable_internal_clock(host);



	return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);

}



static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value)

{

	u32 scratch_32;



	pci_read_config_dword(chip->pdev,

			      O2_SD_PLL_SETTING, &scratch_32);



	scratch_32 &= 0x0000FFFF;

	scratch_32 |= value;



	pci_write_config_dword(chip->pdev,

			       O2_SD_PLL_SETTING, scratch_32);

}



static void sdhci_o2_set_tuning_mode(struct sdhci_host *host)

{

	u16 reg;
@@ -136,19 +230,6 @@ static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode) 
	return 0;

}



static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value)

{

	u32 scratch_32;

	pci_read_config_dword(chip->pdev,

			      O2_SD_PLL_SETTING, &scratch_32);



	scratch_32 &= 0x0000FFFF;

	scratch_32 |= value;



	pci_write_config_dword(chip->pdev,

			       O2_SD_PLL_SETTING, scratch_32);

}



static void o2_pci_led_enable(struct sdhci_pci_chip *chip)

{

	int ret;
@@ -284,86 +365,6 @@ static void sdhci_pci_o2_enable_msi(struct sdhci_pci_chip *chip, 
	host->irq = pci_irq_vector(chip->pdev, 0);

}



static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host)

{

	ktime_t timeout;

	u32 scratch32;



	/* Wait max 50 ms */

	timeout = ktime_add_ms(ktime_get(), 50);

	while (1) {

		bool timedout = ktime_after(ktime_get(), timeout);



		scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE);

		if ((scratch32 & SDHCI_CARD_PRESENT) >> SDHCI_CARD_PRES_SHIFT

		    == (scratch32 & SDHCI_CD_LVL) >> SDHCI_CD_LVL_SHIFT)

			break;



		if (timedout) {

			pr_err("%s: Card Detect debounce never finished.\n",

			       mmc_hostname(host->mmc));

			sdhci_dumpregs(host);

			return;

		}

		udelay(10);

	}

}



static void sdhci_o2_enable_internal_clock(struct sdhci_host *host)

{

	ktime_t timeout;

	u16 scratch;

	u32 scratch32;



	/* PLL software reset */

	scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);

	scratch32 |= O2_PLL_SOFT_RESET;

	sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);

	udelay(1);

	scratch32 &= ~(O2_PLL_SOFT_RESET);

	sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);



	/* PLL force active */

	scratch32 |= O2_PLL_FORCE_ACTIVE;

	sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);



	/* Wait max 20 ms */

	timeout = ktime_add_ms(ktime_get(), 20);

	while (1) {

		bool timedout = ktime_after(ktime_get(), timeout);



		scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1);

		if (scratch & O2_PLL_LOCK_STATUS)

			break;

		if (timedout) {

			pr_err("%s: Internal clock never stabilised.\n",

			       mmc_hostname(host->mmc));

			sdhci_dumpregs(host);

			goto out;

		}

		udelay(10);

	}



	/* Wait for card detect finish */

	udelay(1);

	sdhci_o2_wait_card_detect_stable(host);



out:

	/* Cancel PLL force active */

	scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);

	scratch32 &= ~O2_PLL_FORCE_ACTIVE;

	sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);

}



static int sdhci_o2_get_cd(struct mmc_host *mmc)

{

	struct sdhci_host *host = mmc_priv(mmc);



	sdhci_o2_enable_internal_clock(host);



	return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);

}



static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk)

{

	/* Enable internal clock */