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Commit 90327e7d authored by Greg Rose's avatar Greg Rose Committed by Jeff Kirsher
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i40evf: A0 silicon specific 



A0 stepping silicon specific code

Signed-off-by: default avatarGreg Rose <gregory.v.rose@intel.com>
Tested-by: default avatarSibai Li <sibai.li@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 105bf2fe

drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h

+26 −2
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ 


#define I40E_FW_API_VERSION_MAJOR  0x0001

#define I40E_FW_API_VERSION_MINOR  0x0001

#define I40E_FW_API_VERSION_A0_MINOR  0x0000



struct i40e_aq_desc {

	__le16 flags;
@@ -1198,6 +1199,9 @@ struct i40e_aqc_add_remove_cloud_filters_element_data { 
#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT                 0

#define I40E_AQC_ADD_CLOUD_FILTER_MASK                  (0x3F << \

					I40E_AQC_ADD_CLOUD_FILTER_SHIFT)

#define I40E_AQC_ADD_CLOUD_FILTER_OIP_GRE               0x0002

#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_GRE        0x0004

#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_VNL        0x0007

/* 0x0000 reserved */

#define I40E_AQC_ADD_CLOUD_FILTER_OIP                   0x0001

/* 0x0002 reserved */
@@ -1977,7 +1981,9 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 
struct i40e_aqc_remove_udp_tunnel {

	u8     reserved[2];

	u8     index; /* 0 to 15 */

	u8     reserved2[13];

	u8     pf_filters;

	u8     total_filters;

	u8     reserved2[11];

};



I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
@@ -1987,13 +1993,31 @@ struct i40e_aqc_del_udp_tunnel_completion { 
	u8     index; /* 0 to 15 */

	u8     multiple_pfs;

	u8     total_filters_used;

	u8     reserved1[11];

	u8     reserved;

	u8     tunnels_free;

	u8     reserved1[9];

};



I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);



/* tunnel key structure 0x0B10 */



struct i40e_aqc_tunnel_key_structure_A0 {

	__le16     key1_off;

	__le16     key1_len;

	__le16     key2_off;

	__le16     key2_len;

	__le16     flags;

#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01

/* response flags */

#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS    0x01

#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED   0x02

#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03

	u8         resreved[6];

};



I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure_A0);



struct i40e_aqc_tunnel_key_structure {

	u8	key1_off;

	u8	key2_off;

drivers/net/ethernet/intel/i40evf/i40e_lan_hmc.h

+1 −1
Original line number Diff line number Diff line
@@ -109,7 +109,7 @@ enum i40e_hmc_lan_object_size { 
#define I40E_HMC_L2OBJ_BASE_ALIGNMENT 512

#define I40E_HMC_OBJ_SIZE_TXQ         128

#define I40E_HMC_OBJ_SIZE_RXQ         32

#define I40E_HMC_OBJ_SIZE_FCOE_CNTX   64

#define I40E_HMC_OBJ_SIZE_FCOE_CNTX   128

#define I40E_HMC_OBJ_SIZE_FCOE_FILT   64



enum i40e_hmc_lan_rsrc_type {

drivers/net/ethernet/intel/i40evf/i40e_register.h

+9 −3
Original line number Diff line number Diff line
@@ -186,7 +186,7 @@ 
#define I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_MASK (0xFF << I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_SHIFT)

#define I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_SHIFT 24

#define I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_MASK (0xFF << I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_SHIFT)

#define I40E_PFCM_LANCTXCTL 0x0010C300

#define I40E_PFCM_LANCTXCTL(_pf) (0x0010C300 + ((_pf) * 4))/* _pf=0..15 */

#define I40E_PFCM_LANCTXCTL_QUEUE_NUM_SHIFT 0

#define I40E_PFCM_LANCTXCTL_QUEUE_NUM_MASK (0xFFF << I40E_PFCM_LANCTXCTL_QUEUE_NUM_SHIFT)

#define I40E_PFCM_LANCTXCTL_SUB_LINE_SHIFT 12
@@ -195,11 +195,11 @@ 
#define I40E_PFCM_LANCTXCTL_QUEUE_TYPE_MASK (0x3 << I40E_PFCM_LANCTXCTL_QUEUE_TYPE_SHIFT)

#define I40E_PFCM_LANCTXCTL_OP_CODE_SHIFT 17

#define I40E_PFCM_LANCTXCTL_OP_CODE_MASK (0x3 << I40E_PFCM_LANCTXCTL_OP_CODE_SHIFT)

#define I40E_PFCM_LANCTXDATA(_i) (0x0010C100 + ((_i) * 128)) /* _i=0...3 */

#define I40E_PFCM_LANCTXDATA(_i, _pf) (0x0010C100 + ((_i) * 4) + ((_pf) * 16))/* _i=0...3 _pf=0..15 */

#define I40E_PFCM_LANCTXDATA_MAX_INDEX 3

#define I40E_PFCM_LANCTXDATA_DATA_SHIFT 0

#define I40E_PFCM_LANCTXDATA_DATA_MASK (0xFFFFFFFF << I40E_PFCM_LANCTXDATA_DATA_SHIFT)

#define I40E_PFCM_LANCTXSTAT 0x0010C380

#define I40E_PFCM_LANCTXSTAT(_pf) (0x0010C380 + ((_pf) * 4))/* _pf=0..15 */

#define I40E_PFCM_LANCTXSTAT_CTX_DONE_SHIFT 0

#define I40E_PFCM_LANCTXSTAT_CTX_DONE_MASK (0x1 << I40E_PFCM_LANCTXSTAT_CTX_DONE_SHIFT)

#define I40E_PFCM_LANCTXSTAT_CTX_MISS_SHIFT 1
@@ -2206,6 +2206,12 @@ 
#define I40E_GLPCI_PCIERR 0x000BE4FC

#define I40E_GLPCI_PCIERR_PCIE_ERR_REP_SHIFT 0

#define I40E_GLPCI_PCIERR_PCIE_ERR_REP_MASK (0xFFFFFFFF << I40E_GLPCI_PCIERR_PCIE_ERR_REP_SHIFT)

#define I40E_GLPCI_PCITEST2 0x000BE4BC

#define I40E_GLPCI_PCITEST2_IOV_TEST_MODE_SHIFT 0

#define I40E_GLPCI_PCITEST2_IOV_TEST_MODE_MASK (0x1 << I40E_GLPCI_PCITEST2_IOV_TEST_MODE_SHIFT)

#define I40E_GLPCI_PCITEST2_TAG_ALLOC_SHIFT 1

#define I40E_GLPCI_PCITEST2_TAG_ALLOC_MASK (0x1 << I40E_GLPCI_PCITEST2_TAG_ALLOC_SHIFT)



#define I40E_GLPCI_PKTCT 0x0009C4BC

#define I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_SHIFT 0

#define I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_MASK (0xFFFFFFFF << I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_SHIFT)