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Commit 902cb3c0 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: Adding fastrpc and cdsp device nodes"

parents a5dab5e3 52fbca3a

qcom/holi.dtsi

+124 −0
Original line number Diff line number Diff line
@@ -321,6 +321,14 @@ 
			size = <0x0 0x2000000>;

			linux,cma-default;

		};



		adsp_mem: adsp_region {

			compatible = "shared-dma-pool";

			alloc-ranges = <0 0x00000000 0 0xffffffff>;

			reusable;

			alignment = <0 0x400000>;

			size = <0 0x800000>;

		};

	};



	soc: soc { };
@@ -961,6 +969,122 @@ 
		status = "disabled";

	};



	qcom,msm-cdsp-loader {

		compatible = "qcom,cdsp-loader";

		qcom,proc-img-to-load = "cdsp";

	};



	qcom,msm-adsprpc-mem {

		compatible = "qcom,msm-adsprpc-mem-region";

		memory-region = <&adsp_mem>;

		restrict-access;

	};



	qcom,msm_fastrpc {

		compatible = "qcom,msm-fastrpc-compute";

		qcom,rpc-latency-us = <611>;

		qcom,adsp-remoteheap-vmid = <22 37>;

		qcom,fastrpc-adsp-audio-pdr;

		qcom,fastrpc-adsp-sensors-pdr;



		qcom,msm_fastrpc_compute_cb1 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "cdsprpc-smd";

			iommus = <&apps_smmu 0x1001 0x0000>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable", "HUPCF";

		};



		qcom,msm_fastrpc_compute_cb2 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "cdsprpc-smd";

			iommus = <&apps_smmu 0x1002 0x0000>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable", "HUPCF";

		};



		qcom,msm_fastrpc_compute_cb3 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "cdsprpc-smd";

			iommus = <&apps_smmu 0x1003 0x0000>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable", "HUPCF";

		};



		qcom,msm_fastrpc_compute_cb4 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "cdsprpc-smd";

			iommus = <&apps_smmu 0x1004 0x0000>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable", "HUPCF";

		};



		qcom,msm_fastrpc_compute_cb5 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "cdsprpc-smd";

			iommus = <&apps_smmu 0x1005 0x0000>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable", "HUPCF";

		};



		qcom,msm_fastrpc_compute_cb6 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "cdsprpc-smd";

			iommus = <&apps_smmu 0x1006 0x0000>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable", "HUPCF";

		};



		qcom,msm_fastrpc_compute_cb9 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "cdsprpc-smd";

			qcom,secure-context-bank;

			iommus = <&apps_smmu 0x1009 0x0000>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable", "HUPCF";

		};



		qcom,msm_fastrpc_compute_cb10 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "adsprpc-smd";

			iommus = <&apps_smmu 0x00A3 0x0000>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable", "HUPCF";

		};



		qcom,msm_fastrpc_compute_cb11 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "adsprpc-smd";

			iommus = <&apps_smmu 0x00A4 0x0000>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable", "HUPCF";

		};



		qcom,msm_fastrpc_compute_cb12 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "adsprpc-smd";

			iommus = <&apps_smmu 0x00A5 0x0000>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable", "HUPCF";

		};



		qcom,msm_fastrpc_compute_cb13 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "adsprpc-smd";

			iommus = <&apps_smmu 0x00A6 0x0000>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable", "HUPCF";

		};



		qcom,msm_fastrpc_compute_cb14 {

			compatible = "qcom,msm-fastrpc-compute-cb";

			label = "adsprpc-smd";

			iommus = <&apps_smmu 0x00A7 0x0000>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable", "HUPCF";

		};

	};



	ufshc_mem: ufshc@4804000 {

		compatible = "qcom,ufshc";

		reg = <0x4804000 0x3000>;