Merge "dt-bindings: regulator: add gdsc-regulator bindings"

Qualcomm Technologies, Inc. Always On Processor Clock controller Binding

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Required properties :

- compatible : must be "qcom,aop-qmp-clk"

- #clock-cells : must contain 1

- mboxes : list of QMP mailbox phandle and channel identifier tuples.

- mbox-names: List of identifier strings for each mailbox channel.

		Must contain "qdss_clk".

Example :

	clock_qdss: qcom,aopclk {

		compatible = "qcom,aop-qmp-clk";

		#clock-cells = <1>;

		mboxes = <&qmp_aop 0>;

		mbox-names = "qdss_clk";

	};

QTI Global Distributed Switch Controller (GDSC) Regulator Driver

The GDSC driver, implemented under the regulator framework, is responsible for

safely collapsing and restoring power to peripheral and multimedia cores on

chipsets like SDM845 for power savings.

Required properties:

 - compatible:      Must be "qcom,gdsc"

 - regulator-name:  A string used as a descriptive name for regulator outputs

 - reg:             The address of the GDSCR register

Optional properties:

 - parent-supply:   phandle to the parent supply/regulator node

 - clock-names:     List of string names for core clocks

 - qcom,skip-logic-collapse: Presence denotes a requirement to leave power to

                             the core's logic enabled.

 - qcom,support-hw-trigger: Presence denotes a hardware feature to switch

			    on/off this regulator based on internal HW signals

			    to save more power.

 - qcom,enable-root-clk: Presence denotes that the clocks in the "clocks"

			property are required to be enabled before gdsc is

			turned on and disabled before turning off gdsc. This

			will be used in subsystems where reset is synchronous

			and root clk is active without sw being aware of its

			state. The clock-name which denotes the root clock

			should be named as "core_root_clk".

 - qcom,force-enable-root-clk: If set, denotes that the root clock should be

			force enabled before turning on the GDSC and then be

			immediately force disabled. Likewise for GDSC disable.

			This is used in cases where the core root clock needs

			to be force-enabled prior to turning on the core. The

			clock-name which denotes the root clock should be

			"core_root_clk".

 - qcom,clk-dis-wait-val: Input value for CLK_DIS_WAIT controls state transition

			 delay after halting clock in the collapsible core.

 - reg-names:		Names of the bases for the above "reg" registers.

			Ex. "base", "domain-addr", "sw-reset", "hw-ctrl-addr".

 - qcom,no-status-check-on-disable: Do not poll the status bit when GDSC

			is disabled.

 - qcom,gds-timeout:	Maximum time (in usecs) that might be taken by a GDSC

			to enable.

 - qcom,reset-aon-logic: If present, the GPU DEMET cells need to be reset while

			 enabling the GX GDSC.

 - resets: reset specifier pair consisting of phandle for the reset controller

			and reset lines used by this controller. These can be

			supplied only if we support qcom,skip-logic-collapse.

 - reset-names: reset signal name strings sorted in the same order as the resets

			property. These can be supplied only if we support

			qcom,skip-logic-collapse.

Example:

	gdsc_oxili_gx: qcom,gdsc@fd8c4024 {

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_oxili_gx";

		parent-supply = <&pm8841_s4>;

		reg = <0xfd8c4024 0x4>;

		clock-names = "core_clk";

	};