spi/bfin_spi: use the SPI namespaced bit names (90008a64) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/spi/spi_bfin5xx.c

+11 −10

Original line number	Original line	Diff line number	Diff line
	@@ -504,8 +504,8 @@ static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id)
	* register until it goes low for 2 successive reads		* register until it goes low for 2 successive reads
	*/		*/
	if (drv_data->tx != NULL) {		if (drv_data->tx != NULL) {
	while ((read_STAT(drv_data) & TXS) \|\|		while ((read_STAT(drv_data) & BIT_STAT_TXS) \|\|
	(read_STAT(drv_data) & TXS))		(read_STAT(drv_data) & BIT_STAT_TXS))
	cpu_relax();		cpu_relax();
	}		}

	@@ -514,14 +514,14 @@ static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id)
	dmastat, read_STAT(drv_data));		dmastat, read_STAT(drv_data));

	timeout = jiffies + HZ;		timeout = jiffies + HZ;
	while (!(read_STAT(drv_data) & SPIF))		while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
	if (!time_before(jiffies, timeout)) {		if (!time_before(jiffies, timeout)) {
	dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF");		dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF");
	break;		break;
	} else		} else
	cpu_relax();		cpu_relax();

	if ((dmastat & DMA_ERR) && (spistat & RBSY)) {		if ((dmastat & DMA_ERR) && (spistat & BIT_STAT_RBSY)) {
	msg->state = ERROR_STATE;		msg->state = ERROR_STATE;
	dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");		dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");
	} else {		} else {
	@@ -1000,11 +1000,12 @@ static int bfin_spi_setup(struct spi_device *spi)
	if (chip_info) {		if (chip_info) {
	/* Make sure people stop trying to set fields via ctl_reg		/* Make sure people stop trying to set fields via ctl_reg
	* when they should actually be using common SPI framework.		* when they should actually be using common SPI framework.
	* Currently we let through: WOM EMISO PSSE GM SZ TIMOD.		* Currently we let through: WOM EMISO PSSE GM SZ.
	* Not sure if a user actually needs/uses any of these,		* Not sure if a user actually needs/uses any of these,
	* but let's assume (for now) they do.		* but let's assume (for now) they do.
	*/		*/
	if (chip_info->ctl_reg & (SPE\|MSTR\|CPOL\|CPHA\|LSBF\|SIZE)) {		if (chip_info->ctl_reg & ~(BIT_CTL_OPENDRAIN \| BIT_CTL_EMISO \| \
			BIT_CTL_PSSE \| BIT_CTL_GM \| BIT_CTL_SZ)) {
	dev_err(&spi->dev, "do not set bits in ctl_reg "		dev_err(&spi->dev, "do not set bits in ctl_reg "
	"that the SPI framework manages\n");		"that the SPI framework manages\n");
	goto error;		goto error;
	@@ -1022,13 +1023,13 @@ static int bfin_spi_setup(struct spi_device *spi)

	/* translate common spi framework into our register */		/* translate common spi framework into our register */
	if (spi->mode & SPI_CPOL)		if (spi->mode & SPI_CPOL)
	chip->ctl_reg \|= CPOL;		chip->ctl_reg \|= BIT_CTL_CPOL;
	if (spi->mode & SPI_CPHA)		if (spi->mode & SPI_CPHA)
	chip->ctl_reg \|= CPHA;		chip->ctl_reg \|= BIT_CTL_CPHA;
	if (spi->mode & SPI_LSB_FIRST)		if (spi->mode & SPI_LSB_FIRST)
	chip->ctl_reg \|= LSBF;		chip->ctl_reg \|= BIT_CTL_LSBF;
	/* we dont support running in slave mode (yet?) */		/* we dont support running in slave mode (yet?) */
	chip->ctl_reg \|= MSTR;		chip->ctl_reg \|= BIT_CTL_MASTER;

	/*		/*
	* Notice: for blackfin, the speed_hz is the value of register		* Notice: for blackfin, the speed_hz is the value of register