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Commit 8ff19db9 authored by Yoshihiro Shimoda's avatar Yoshihiro Shimoda Committed by Greg Kroah-Hartman
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clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag 

[ Upstream commit ffbf9cf3f9460e320c3f1a90a51145da86c16781 ]

Geert suggested defining multiple register layout variants using an enum
[1] to support further devices like R-Car V3U.  So, use enum
clk_reg_layout instead of a boolean .stbyctrl flag.  No behavioral
change.

[1] https://lore.kernel.org/linux-renesas-soc/CAMuHMdVAgN69p9FFnQdO4iHk2CHkeNaVui2Q-FOY6_BFVjQ-Nw@mail.gmail.com/



Signed-off-by: default avatarYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/1599810232-29035-2-git-send-email-yoshihiro.shimoda.uh@renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Stable-dep-of: 1c052043c79a ("clk: renesas: cpg-mssr: Remove superfluous check in resume code")
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 330b7094

drivers/clk/renesas/r7s9210-cpg-mssr.c

+1 −1
Original line number Diff line number Diff line
@@ -213,7 +213,7 @@ const struct cpg_mssr_info r7s9210_cpg_mssr_info __initconst = { 
	.cpg_clk_register = rza2_cpg_clk_register,



	/* RZ/A2 has Standby Control Registers */

	.stbyctrl = true,

	.reg_layout = CLK_REG_LAYOUT_RZ_A,

};



static void __init r7s9210_cpg_mssr_early_init(struct device_node *np)

drivers/clk/renesas/renesas-cpg-mssr.c

+14 −13
Original line number Diff line number Diff line
@@ -111,12 +111,12 @@ static const u16 srcr[] = { 
 * @rcdev: Optional reset controller entity

 * @dev: CPG/MSSR device

 * @base: CPG/MSSR register block base address

 * @reg_layout: CPG/MSSR register layout

 * @rmw_lock: protects RMW register accesses

 * @np: Device node in DT for this CPG/MSSR module

 * @num_core_clks: Number of Core Clocks in clks[]

 * @num_mod_clks: Number of Module Clocks in clks[]

 * @last_dt_core_clk: ID of the last Core Clock exported to DT

 * @stbyctrl: This device has Standby Control Registers

 * @notifiers: Notifier chain to save/restore clock state for system resume

 * @smstpcr_saved[].mask: Mask of SMSTPCR[] bits under our control

 * @smstpcr_saved[].val: Saved values of SMSTPCR[]
@@ -128,13 +128,13 @@ struct cpg_mssr_priv { 
#endif

	struct device *dev;

	void __iomem *base;

	enum clk_reg_layout reg_layout;

	spinlock_t rmw_lock;

	struct device_node *np;



	unsigned int num_core_clks;

	unsigned int num_mod_clks;

	unsigned int last_dt_core_clk;

	bool stbyctrl;



	struct raw_notifier_head notifiers;

	struct {
@@ -177,7 +177,7 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable) 
		enable ? "ON" : "OFF");

	spin_lock_irqsave(&priv->rmw_lock, flags);



	if (priv->stbyctrl) {

	if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {

		value = readb(priv->base + STBCR(reg));

		if (enable)

			value &= ~bitmask;
@@ -199,7 +199,7 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable) 


	spin_unlock_irqrestore(&priv->rmw_lock, flags);



	if (!enable || priv->stbyctrl)

	if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A)

		return 0;



	for (i = 1000; i > 0; --i) {
@@ -233,7 +233,7 @@ static int cpg_mstp_clock_is_enabled(struct clk_hw *hw) 
	struct cpg_mssr_priv *priv = clock->priv;

	u32 value;



	if (priv->stbyctrl)

	if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)

		value = readb(priv->base + STBCR(clock->index / 32));

	else

		value = readl(priv->base + MSTPSR(clock->index / 32));
@@ -272,7 +272,7 @@ struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec, 


	case CPG_MOD:

		type = "module";

		if (priv->stbyctrl) {

		if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {

			idx = MOD_CLK_PACK_10(clkidx);

			range_check = 7 - (clkidx % 10);

		} else {
@@ -800,7 +800,8 @@ static int cpg_mssr_suspend_noirq(struct device *dev) 
	/* Save module registers with bits under our control */

	for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {

		if (priv->smstpcr_saved[reg].mask)

			priv->smstpcr_saved[reg].val = priv->stbyctrl ?

			priv->smstpcr_saved[reg].val =

				priv->reg_layout == CLK_REG_LAYOUT_RZ_A ?

				readb(priv->base + STBCR(reg)) :

				readl(priv->base + SMSTPCR(reg));

	}
@@ -830,7 +831,7 @@ static int cpg_mssr_resume_noirq(struct device *dev) 
		if (!mask)

			continue;



		if (priv->stbyctrl)

		if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)

			oldval = readb(priv->base + STBCR(reg));

		else

			oldval = readl(priv->base + SMSTPCR(reg));
@@ -839,7 +840,7 @@ static int cpg_mssr_resume_noirq(struct device *dev) 
		if (newval == oldval)

			continue;



		if (priv->stbyctrl) {

		if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {

			writeb(newval, priv->base + STBCR(reg));

			/* dummy read to ensure write has completed */

			readb(priv->base + STBCR(reg));
@@ -862,8 +863,8 @@ static int cpg_mssr_resume_noirq(struct device *dev) 


		if (!i)

			dev_warn(dev, "Failed to enable %s%u[0x%x]\n",

				 priv->stbyctrl ? "STB" : "SMSTP", reg,

				 oldval & mask);

				 priv->reg_layout == CLK_REG_LAYOUT_RZ_A ?

				 "STB" : "SMSTP", reg, oldval & mask);

	}



	return 0;
@@ -911,7 +912,7 @@ static int __init cpg_mssr_common_init(struct device *dev, 
	priv->num_mod_clks = info->num_hw_mod_clks;

	priv->last_dt_core_clk = info->last_dt_core_clk;

	RAW_INIT_NOTIFIER_HEAD(&priv->notifiers);

	priv->stbyctrl = info->stbyctrl;

	priv->reg_layout = info->reg_layout;



	for (i = 0; i < nclks; i++)

		priv->clks[i] = ERR_PTR(-ENOENT);
@@ -991,7 +992,7 @@ static int __init cpg_mssr_probe(struct platform_device *pdev) 
		return error;



	/* Reset Controller not supported for Standby Control SoCs */

	if (info->stbyctrl)

	if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)

		return 0;



	error = cpg_mssr_reset_controller_register(priv);

drivers/clk/renesas/renesas-cpg-mssr.h

+7 −5
Original line number Diff line number Diff line
@@ -85,6 +85,11 @@ struct mssr_mod_clk { 


struct device_node;



enum clk_reg_layout {

	CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3 = 0,

	CLK_REG_LAYOUT_RZ_A,

};



    /**

     * SoC-specific CPG/MSSR Description

     *
@@ -105,6 +110,7 @@ struct device_node; 
     * @crit_mod_clks: Array with Module Clock IDs of critical clocks that

     *                 should not be disabled without a knowledgeable driver

     * @num_crit_mod_clks: Number of entries in crit_mod_clks[]

     * @reg_layout: CPG/MSSR register layout from enum clk_reg_layout

     *

     * @core_pm_clks: Array with IDs of Core Clocks that are suitable for Power

     *                Management, in addition to Module Clocks
@@ -112,10 +118,6 @@ struct device_node; 
     *

     * @init: Optional callback to perform SoC-specific initialization

     * @cpg_clk_register: Optional callback to handle special Core Clock types

     *

     * @stbyctrl: This device has Standby Control Registers which are 8-bits

     *            wide, no status registers (MSTPSR) and have different address

     *            offsets.

     */



struct cpg_mssr_info {
@@ -130,7 +132,7 @@ struct cpg_mssr_info { 
	unsigned int num_core_clks;

	unsigned int last_dt_core_clk;

	unsigned int num_total_core_clks;

	bool stbyctrl;

	enum clk_reg_layout reg_layout;



	/* Module Clocks */

	const struct mssr_mod_clk *mod_clks;