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Commit 8f60f762 authored by Nikita Danilov's avatar Nikita Danilov Committed by David S. Miller
Browse files

net: aquantia: renaming for better visibility



Removed extra characters from the names of structures to unify prefixes
used through the driver code (we normally use hw_atl for hw specifics).
HW_ATL_B0_ and HW_ATL_A0_ are the same and useless copies.

Signed-off-by: default avatarNikita Danilov <nikita.danilov@aquantia.com>
Signed-off-by: default avatarIgor Russkikh <igor.russkikh@aquantia.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent e9157848
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+2 −2
Original line number Diff line number Diff line
@@ -112,7 +112,7 @@ struct aq_hw_s {
	const struct aq_fw_ops *aq_fw_ops;
	void __iomem *mmio;
	struct aq_hw_link_status_s aq_link_status;
	struct hw_aq_atl_utils_mbox mbox;
	struct hw_atl_utils_mbox mbox;
	struct hw_atl_stats_s last_stats;
	struct aq_stats_s curr_stats;
	u64 speed;
@@ -124,7 +124,7 @@ struct aq_hw_s {
	u32 mbox_addr;
	u32 rpc_addr;
	u32 rpc_tid;
	struct hw_aq_atl_utils_fw_rpc rpc;
	struct hw_atl_utils_fw_rpc rpc;
};

struct aq_ring_s;
+16 −16
Original line number Diff line number Diff line
@@ -49,37 +49,37 @@
const struct aq_hw_caps_s hw_atl_a0_caps_aqc100 = {
	DEFAULT_A0_BOARD_BASIC_CAPABILITIES,
	.media_type = AQ_HW_MEDIA_TYPE_FIBRE,
	.link_speed_msk = HW_ATL_A0_RATE_5G |
			  HW_ATL_A0_RATE_2G5 |
			  HW_ATL_A0_RATE_1G |
			  HW_ATL_A0_RATE_100M,
	.link_speed_msk = AQ_NIC_RATE_5G |
			  AQ_NIC_RATE_2GS |
			  AQ_NIC_RATE_1G |
			  AQ_NIC_RATE_100M,
};

const struct aq_hw_caps_s hw_atl_a0_caps_aqc107 = {
	DEFAULT_A0_BOARD_BASIC_CAPABILITIES,
	.media_type = AQ_HW_MEDIA_TYPE_TP,
	.link_speed_msk = HW_ATL_A0_RATE_10G |
			  HW_ATL_A0_RATE_5G |
			  HW_ATL_A0_RATE_2G5 |
			  HW_ATL_A0_RATE_1G |
			  HW_ATL_A0_RATE_100M,
	.link_speed_msk = AQ_NIC_RATE_10G |
			  AQ_NIC_RATE_5G |
			  AQ_NIC_RATE_2GS |
			  AQ_NIC_RATE_1G |
			  AQ_NIC_RATE_100M,
};

const struct aq_hw_caps_s hw_atl_a0_caps_aqc108 = {
	DEFAULT_A0_BOARD_BASIC_CAPABILITIES,
	.media_type = AQ_HW_MEDIA_TYPE_TP,
	.link_speed_msk = HW_ATL_A0_RATE_5G  |
			  HW_ATL_A0_RATE_2G5 |
			  HW_ATL_A0_RATE_1G  |
			  HW_ATL_A0_RATE_100M,
	.link_speed_msk = AQ_NIC_RATE_5G |
			  AQ_NIC_RATE_2GS |
			  AQ_NIC_RATE_1G |
			  AQ_NIC_RATE_100M,
};

const struct aq_hw_caps_s hw_atl_a0_caps_aqc109 = {
	DEFAULT_A0_BOARD_BASIC_CAPABILITIES,
	.media_type = AQ_HW_MEDIA_TYPE_TP,
	.link_speed_msk = HW_ATL_A0_RATE_2G5 |
			  HW_ATL_A0_RATE_1G |
			  HW_ATL_A0_RATE_100M,
	.link_speed_msk = AQ_NIC_RATE_2GS |
			  AQ_NIC_RATE_1G |
			  AQ_NIC_RATE_100M,
};

static int hw_atl_a0_hw_reset(struct aq_hw_s *self)
+0 −6
Original line number Diff line number Diff line
@@ -62,12 +62,6 @@
#define HW_ATL_A0_MPI_SPEED_MSK       0xFFFFU
#define HW_ATL_A0_MPI_SPEED_SHIFT     16U

#define HW_ATL_A0_RATE_10G            BIT(0)
#define HW_ATL_A0_RATE_5G             BIT(1)
#define HW_ATL_A0_RATE_2G5            BIT(3)
#define HW_ATL_A0_RATE_1G             BIT(4)
#define HW_ATL_A0_RATE_100M           BIT(5)

#define HW_ATL_A0_TXBUF_MAX 160U
#define HW_ATL_A0_RXBUF_MAX 320U

+17 −17
Original line number Diff line number Diff line
@@ -51,38 +51,38 @@
const struct aq_hw_caps_s hw_atl_b0_caps_aqc100 = {
	DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
	.media_type = AQ_HW_MEDIA_TYPE_FIBRE,
	.link_speed_msk = HW_ATL_B0_RATE_10G |
			  HW_ATL_B0_RATE_5G |
			  HW_ATL_B0_RATE_2G5 |
			  HW_ATL_B0_RATE_1G |
			  HW_ATL_B0_RATE_100M,
	.link_speed_msk = AQ_NIC_RATE_10G |
			  AQ_NIC_RATE_5G |
			  AQ_NIC_RATE_2GS |
			  AQ_NIC_RATE_1G |
			  AQ_NIC_RATE_100M,
};

const struct aq_hw_caps_s hw_atl_b0_caps_aqc107 = {
	DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
	.media_type = AQ_HW_MEDIA_TYPE_TP,
	.link_speed_msk = HW_ATL_B0_RATE_10G |
			  HW_ATL_B0_RATE_5G |
			  HW_ATL_B0_RATE_2G5 |
			  HW_ATL_B0_RATE_1G |
			  HW_ATL_B0_RATE_100M,
	.link_speed_msk = AQ_NIC_RATE_10G |
			  AQ_NIC_RATE_5G |
			  AQ_NIC_RATE_2GS |
			  AQ_NIC_RATE_1G |
			  AQ_NIC_RATE_100M,
};

const struct aq_hw_caps_s hw_atl_b0_caps_aqc108 = {
	DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
	.media_type = AQ_HW_MEDIA_TYPE_TP,
	.link_speed_msk = HW_ATL_B0_RATE_5G |
			  HW_ATL_B0_RATE_2G5 |
			  HW_ATL_B0_RATE_1G |
			  HW_ATL_B0_RATE_100M,
	.link_speed_msk = AQ_NIC_RATE_5G |
			  AQ_NIC_RATE_2GS |
			  AQ_NIC_RATE_1G |
			  AQ_NIC_RATE_100M,
};

const struct aq_hw_caps_s hw_atl_b0_caps_aqc109 = {
	DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
	.media_type = AQ_HW_MEDIA_TYPE_TP,
	.link_speed_msk = HW_ATL_B0_RATE_2G5 |
			  HW_ATL_B0_RATE_1G |
			  HW_ATL_B0_RATE_100M,
	.link_speed_msk = AQ_NIC_RATE_2GS |
			  AQ_NIC_RATE_1G |
			  AQ_NIC_RATE_100M,
};

static int hw_atl_b0_hw_reset(struct aq_hw_s *self)
+0 −6
Original line number Diff line number Diff line
@@ -67,12 +67,6 @@
#define HW_ATL_B0_MPI_SPEED_MSK         0xFFFFU
#define HW_ATL_B0_MPI_SPEED_SHIFT       16U

#define HW_ATL_B0_RATE_10G              BIT(0)
#define HW_ATL_B0_RATE_5G               BIT(1)
#define HW_ATL_B0_RATE_2G5              BIT(3)
#define HW_ATL_B0_RATE_1G               BIT(4)
#define HW_ATL_B0_RATE_100M             BIT(5)

#define HW_ATL_B0_TXBUF_MAX  160U
#define HW_ATL_B0_RXBUF_MAX  320U

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